LMH0318_15 Datasheet, PDF (5/57 Pages) Texas Instruments – LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver

www.ti.com
LMH0318
SNLS508 – SEPTEMBER 2015
Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
PIN
I/O
NAME
NO.
DESCRIPTION
MODE_SEL
1
Input, 4-Level
Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up
ADDR0
ADDR1
2
4-level strap pins used to set the SMBus address of the device. The pin
state is read on power-up. The multi-level nature of these pins allows for
16 unique device addresses. Note SMBus section for further details. The
four strap options include:
1 kΩ to VDD:
Input, 4-Level • Represents logic state 11’b
15
Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17
20 kΩ to GND:
• Represents logic state 01'b
1 kΩ to GND:
• Represents logic state 00'b
SMBus clock input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is
SCL
3
Input, 2-Level required as per SMBus interface standard. This pin is 3.3 V LVCMOS
tolerant.
SDA
4
I/O, Open Drain, 2-
Level
SMBus data input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is
required as per SMBus interface standard. This pin is 3.3 V LVCMOS
tolerant.
RESERVED
5,14,17,
18
No Connect
ENABLE
Powers down device when pulled low
1 kΩ to VDD:
• Power down until valid signal detected
Float(Default): Reserved
6
Input, 4-Level 20 kΩ to GND:
• Reserved
1 kΩ to GND:
• Power down including signal detects and Reset Registers upon
power-up
LOS_INT_N
Output, LVCMOS Programmable Interrupt caused by change in LOS, violation of internal
13
Open Drain, 2- eye monitor threshold, change in lock. External 4.7-kΩ pull-up resistor is
Level
required. This pin is 3.3 V LVCMOS tolerant.
LOCK
Indicates CDR lock Status
High:
16
Output, 2.5 V
LVCMOS, 2-Level
• CDR locked
Low:
• CDR not locked
HIGH SPEED DIFFERENTIAL I/O
IN0+
IN0-
11
Input, Analog Inverting and non-inverting differential inputs. An on-chip 100 Ω
terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC
12
Input, Analog _{coupling capacitors.}
IN1+
IN1-
8
Input, Analog Inverting and non-inverting differential inputs. An on-chip 100 Ω
terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC
9
Input, Analog _{coupling capacitors.}
OUT0+
OUT0-
20
Output, 75 Ω CML
Compatible
Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating
resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC
19
Output, 75 Ω CML _{coupling capacitors}
Compatible
OUT1+
OUT1-
23
Output, Analog Inverting and non-inverting differential outputs. An on-chip 100 Ω
terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC
22
Output, Analog _{coupling capacitors}
VDD
7, 21
2.5 V Supply 2.5V ± 5%
VSS
10, 24
Ground
Connect directly to ground (GND)
DAP
Ground
Exposed DAP, connect to GND using at least 5 vias (see Figure 23 )
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: LMH0318
Submit Documentation Feedback
5