LMH0318_15 Datasheet, PDF (43/57 Pages) Texas Instruments – LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver

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9 Application and Implementation
LMH0318
SNLS508 – SEPTEMBER 2015
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMH0318 is a single channel SDI reclocker with integrated cable driver that supports different application
spaces. The following sections describe the typical use cases and common implementation practices.
9.1.1 General Guidance for All Applications
The LMH0318 supports two modes of configuration: SPI Mode, and SMBus Mode. Once one of these two control
mechanism is chosen, pay attention to the PCB layout for the high speed signals. The LMH0318 has strong
equalization capabilities that allow it to recover data over lossy channels. As a result, the optimal placement for
the LMH0318 is with the higher loss channel at its input and lower loss channel segment at the output in order to
meet the various SMPTE requirements. The SMPTE specifications also define the use of AC coupling capacitors
for transporting uncompressed serial data streams with heavy low frequency content. This specification requires
the use of a 4.7 µF AC coupling capacitor to avoid low frequency DC wander. The 75 Ω signal is also required to
meet certain rise/fall timing to facilitate highest eye opening for the receiving device. The LMH0318 built-in 75 Ω
termination minimizes parasitic, improving overall signal integrity. Note: When the FPGA is not transmitting valid
SMPTE data, the FPGA output should be muted (P=N).
9.2 Typical Application
VDD
VDD
VDD
FPGA
FPGA
ENABLE
.:
MODE_SEL
.:
0.01 PF
0.01 PF
OUT
6
11
IN0+
100: Differential T-Line ^{4.7 PF}
OUT
12
IN0-
OUT
8 _IN1+
100: Differential T-Line _{4.7 PF}
OUT
9 _IN1-
SS_N
2
1
7 21
4.7 PF
OUT0+ ₂₀
:T-Line
LMH0318
OUT0- ₁₉
DAP
VSS ₂₄
VSS ₁₀
4.7 PF
:
4.7 PF
OUT1+
IN+
23
100: Differential T-Line
OUT1-
IN-
22
3 4 13 15 16
SCK
MOSI
LOS_INT_N
MISO
LOCK
Figure 17. LMH0318 SPI Mode Configuration
FPGA
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