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LMH0318_15 Datasheet, PDF (14/57 Pages) Texas Instruments – LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver
LMH0318
SNLS508 – SEPTEMBER 2015
www.ti.com
8.3 Feature Description
The LMH0318 data path consists of several key blocks as shown in the Functional Block Diagram. These key
circuits are:
• Loss of Signal Detector
• Continuous Time Linear Equalizer (CTLE) for FR4 Compensation
• 2:1 Multiplexer/1:2 Fanout
• CDR
• Eye Monitor
• Differential Output Selection
• 75 Ω and 100 Ω Output Drivers
• SMBus/SPI Configuration
8.3.1 Loss of Signal Detector
The LMH0318 supports two high speed differential input ports, with internal 100 Ω terminations. The inputs must
be AC coupled. The external AC coupling capacitor value should take into account the pathological low
frequency content. For most applications, the RC time constant of 4.7 µF AC coupling capacitor plus the 50 Ω
termination resistor is capable of handing the pathological video pattern's low frequency content.
The signal detect circuit is designed to assert when data traffic with a certain minimum amplitude is present at
the input of the device. It is also designed to de-assert, or remain de-asserted, when there is noise below certain
amplitude at the input to the device.
The LMH0318 has two signal detect circuits, one for each input. Each signal detect threshold can be set
independently. By default, both signal detects are powered on. The user selects IN1 or IN0 through SMBus/SPI
interface.
8.3.2 Continuous Time Linear Equalizer (CTLE)
The LMH0318 has receive-side equalization, and a key part is the Continuous Time Linear Equalizer (CTLE).
This circuit operates on the received differential signal and compensates for frequency-dependent loss due to the
transmission media. The CTLE applies gain to the input signal. This gain varies over frequency: higher
frequencies are boosted more than lower frequencies. The CTLE works to restore the input signal to full
amplitude across a wide range of frequencies.
The CTLE consists of 4 stages with each stage having two boost control bits. This allows 256 different boost
settings. CTLE boost levels are determined by summing the boost levels of the 4 stages. The CTLE is configured
manually. See LMH0318 Programming Guide (SNLU183) on how to quickly select the most appropriate CTLE
boost setting.
There are two CTLEs, one for each input, IN0 and IN1. Only one CTLE is enabled at a time, according to the
user input channel selection. If IN0 is selected, the CTLE for IN0 is powered on and the IN1 CTLE is powered
off. The CTLE is able to handle low loss channels without over-equalizing by bypassing the CTLE.
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