DS90UR916Q Datasheet, PDF (8/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

Symbol
Parameter
Conditions
V_OH
High Level Output Voltage I_OH = −2 mA, OS_PCLK/DATA = L
V_OL
Low Level Output Voltage I_OL = +2 mA, OS_PCLK/DATA = L
I_OS
Output Short Circuit Current
V_DDIO = 1.8V
V_OUT = 0V, OS_PCLK/DATA = L/H
Output Short Circuit Current ^{VDDIO = 1.8V}
V_OUT = 0V, OS_PCLK/DATA = L/H
I_OZ
PDB = 0V, OSS_SEL = 0V,
TRI-STATE Output Current _{VOUT = 0V or VDDIO}
LVDS RECEIVER DC SPECIFICATIONS
V_TH
Differential Input Threshold
High Voltage
V_TL
Differential Input Threshold ^{VCM = +1.2V (Internal VBIAS)}
Low Voltage
Common Mode Voltage,
V_CM
Internal V_BIAS
I_IN
Input Current
V_IN = 0V or V_DDIO
R_T
Internal Termination
Resistor
CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
V_OD
Differential Output Voltage R_L = 100Ω
V_OS
Offset Voltage
Single-ended
R_L = 100Ω
R_T
Internal Termination
Resistor
SUPPLY CURRENT
I_DD1
I_DDIO1
I_DDZ
I_DDIOZ
Deserializer
Supply Current
(includes load current)
Checker Board Pattern,
OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON,CMLOUTP/N
enabled
C_L = 4pF, Figure 1
Deserializer Supply Current PDB = 0V, All other
Power Down
LVCMOS Inputs = 0V
V_DD= 1.89V
V_DDIO=1.89V
V_DDIO = 3.6V
V_DD= 1.89V
V_DDIO=1.89V
V_DDIO = 3.6V
Pin/Freq.
R[7:0], G
[7:0], B[7:0],
HS, VS, DE,
PCLK, LOCK,
PASS
PCLK
Des Outputs
Outputs
RIN+, RIN-
CMLOUTP,
CMLOUTN
All V_DD pins
V_DDIO
All V_DD pins
V_DDIO
Min
V_DDIO−
0.45
GND
-15
+50
−50
-15
80
80
Typ
V_DDIO
18
18
1.2
100
542
1.4
100
93
33
62
40
5
10
Max
0.45
+15
+15
120
120
110
45
75
3000
50
100
Units
V
V
mA
mA
µA
mV
mV
V
µA
Ω
mV
V
Ω
mA
mA
mA
µA
µA
µA
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