DS90UR916Q Datasheet, PDF (16/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

Functional Description
The DS90UR905 / DS90UR916Q chipset transmits and re-
ceives 27-bits of data (24-high speed color bits and 3 low
speed video control signals) over a single serial FPD-Link II
pair operating at 140Mbps to 1.82Gbps. The serial stream al-
so contains an embedded clock, video control signals and the
DC-balance information which enhances signal quality and
supports AC coupling. The pair is intended for use with each
other but is backward compatible with previous generations
of FPD-Link II as well.
The Des can attain lock to a data stream without the use of a
separate reference clock source, which greatly simplifies sys-
tem complexity and overall cost. The Des also synchronizes
to the Ser regardless of the data pattern, delivering true au-
tomatic “plug and lock” performance. It can lock to the incom-
ing serial stream without the need of special training patterns
or sync characters. The Des recovers the clock and data by
extracting the embedded clock information, validating and
then deserializing the incoming data stream providing a par-
allel LVCMOS video bus to the display. White balance LUTs
and dithering features are provided to enable display image
enhancement.
The DS90UR905 / DS90UR916Q chipset can operate in 24-
bit color depth (with VS,HS,DE encoded in the DCA bit) or in
18-bit color depth (with VS, HS, DE encoded in DCA or
mapped into the high-speed data bits). In 18–bit color appli-
cations, the three video signals maybe sent encoded via the
DCA bit (restrictions apply) or sent as “data bits” along with
three additional general purpose signals.
Data Transfer
The DS90UR905 / DS90UR916Q chipset will transmit and
receive a pixel of data in the following format: C1 and C0 rep-
resent the embedded clock in the serial stream. C1 is always
HIGH and C0 is always LOW. b[23:0] contain the scrambled
RGB data. DCB is the DC-Balanced control bit. DCB is used
to minimize the short and long-term DC bias on the signal
lines. This bit determines if the data is unmodified or inverted.
DCA is used to validate data integrity in the embedded data
stream and can also contain encoded control (VS,HS,DE).
Both DCA and DCB coding schemes are generated by the
Ser and decoded by the Des automatically. Figure 11 illus-
trates the serial stream per PCLK cycle.
FIGURE 11. FPD-Link II Serial Stream (905/916)
30115637
Des OPERATING MODES AND BACKWARD
COMPATIBILITY (CONFIG[1:0])
The DS90UR916Q is also backward compatible with previous
generations of FPD-Link II. Configuration modes are provided
for backwards compatibility with the DS90C124 FPD-Link II
Generation 1, and also the DS90UR124 FPD-Link II Gener-
ation 2 chipset by setting the respective mode with the CON-
FIG[1:0] pins or control register as shown in Table 1. The
selection also determines whether the Video Control Signal
filter feature is enabled or disabled in Normal mode.
When the DS90UR916 deserializer is configured to operate
in backward compatible modes the image enhancement fea-
tures (white balance and FRC dithering) are not available.
CON
FIG1
L
L
H
H
TABLE 1. DS90UR916Q Des Modes
CON Mode
FIG0
Des Device
L Normal Mode, Control DS90UR905
Signal Filter disabled
H Normal Mode, Control DS90UR905
Signal Filter enabled
L Backwards Compatible DS90UR241
GEN2
H Backwards Compatible DS90C241
GEN1
Video Control Signal Filter
When operating the devices in Normal Mode, the Video Con-
trol Signals (DE, HS, VS) have the following restrictions:
• Normal Mode with Control Signal Filter Enabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are
transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals
with limited transitions. Glitches of a control signal can cause
a visual display error. This feature allows for the chipset to
validate and filter out any high frequency noise on the control
signals. See Figure 12.
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