DS90UR916Q Datasheet, PDF (1/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

DS90UR916Q
February 22, 2012
5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image
Enhancement
General Description
The DS90UR916Q FPD-Link II deserializer operates with the
DS90UR905Q FPD-Link II serializer to deliver 24-bit digital
video data over a single differential pair. The DS90UR916Q
provides features designed to enhance image quality at the
display. The high speed serial bus scheme of FPD-Link II
greatly eases system design by eliminating skew problems
between clock and data, reduces the number of connector
pins, reduces the interconnect size, weight, and cost, and
overall eases PCB layout. In addition, internal DC balanced
decoding is used to support AC-coupled interconnects.
The DS90UR916Q Des (deserializer) recovers the data
(RGB) and control signals and extracts the clock from the se-
rial stream. The Des locks to the incoming serial data stream
without the use of a training sequence or special SYNC pat-
terns, and does not require a reference clock. A link status
(LOCK) output signal is provided. The DS90UR916Q is ide-
ally suited for 24-bit color applications. White balance lookup
tables and adaptive Hi-FRC dithering provide the user a cost-
effective means to enhance display image quality.
Serial transmission is optimized with user selectable receiver
equalization. EMI is minimized by the use of low voltage dif-
ferential signaling, output slew control, and the Des may be
configured to generate Spread Spectrum Clock and Data on
its parallel outputs.
The DS90UR916Qis offered in a 60-pin LLP package. It is
specified over the automotive AEC-Q100 grade 2 tempera-
ture range of -40°C to +105°C.
Features
■ ^{5 – 65 MHz PCLK support (140 Mbps – 1.82 Gbps)}
■ ^{RGB888 + VS, HS, DE support}
■ ^{Image enhancement - White balance LUTs and Adaptive}
Hi-FRC dithering
■ ^{AC coupled STP interconnect cable up to 10 meters}
■ ^{@ Speed link BIST mode and reporting pin}
■ ^{I2C compatible Serial Control Bus}
■ ^{Power down mode minimizes power dissipation}
■ ^{1.8V or 3.3V compatible LVCMOS I/O interface}
■ ^{Automotive grade product: AEC-Q100 Grade 2 qualified}
■ ^{>8 kV HBM and ISO 10605 ESD Rating}
■ ^{FAST random data lock; no reference clock required}
■ ^{Adjustable input receiver equalization}
■ ^{LOCK (real time link status) reporting pin}
■ ^{EMI minimization on output parallel bus (SSCG)}
■ ^{Output Slew control (OS)}
■ ^{Backward compatible mode for operation with older}
generation devices
Applications
■ ^{Automotive Display for Navigation}
■ ^{Automotive Display for Entertainment}
Applications Diagram
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