DS90UR916Q Datasheet, PDF (23/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

OSC_SEL2
L
L
L
L
H
H
H
H
TABLE 7. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
OSC_SEL1
L
L
H
H
L
L
H
H
OSC_SEL0
L
H
L
H
L
H
L
H
PCLK Oscillator Output
Off – Feature Disabled – Default
50 MHz ±40%
25 MHz ±40%
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
8.3 MHz ±40%
6.3 MHz ±40%
30115654
FIGURE 19. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled
OP_LOW — Optional
The OP_ LOW feature is used to hold the LVCMOS outputs
(except the LOCK output) at a LOW state. This feature is en-
abled by setting the OP_LOW strap pin = HIGH, followed by
the rising edge of PDB. The user must toggle the OP_LOW
Set/Reset register bit to release the outputs to the normal
toggling state. Note that the release of the outputs can only
occur when LOCK is HIGH. When the OP_LOW feature is
enabled, anytime LOCK = LOW, the LVCMOS outputs will
toggle to a LOW state again. The OP_ LOW strap pin feature
is assigned to output PASS pin 42.
Restrictions on other straps:
1) Other straps should not be used in order to keep RGB[7:0],
HS, VS, DE, and PCLK at a true LOW state. Other features
should be selected thru I2C.
2) OSS_SEL function is not available when O/P_LOW is tied
H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in
TRI-STATE before PDB toggles HIGH because the OP_LOW
strap value has not been recognized until the DS90UR916
powers up. Figure 20 shows the user controlled release of
OP_LOW and automatic reset of OP_LOW set on the falling
edge of LOCK. Figure 21 shows the user controlled release
of OP_LOW and manual reset of OP_LOW set. Note manual
reset of OP_LOW can only occur when LOCK is H.
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