DS90UR916Q Datasheet, PDF (37/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

TABLE 12. Alternate Color / Data Mapping — See Text Below
18-bit 18-bit 18-bit 24-bit
RGB
RGB
RGB
RGB
0
LSB R0 GP0
RO
0
R1
GP1
R1
R0
R2
R0
R2
R1
R3
R1
R3
R2
R4
R2
R4
R3
MSB R5
R3
R5
R4
LSB G0
R4
R6
R5
G1
R5
R7
0
G2
GP2
G0
0
G3
GP3
G1
G0
G4
G0
G2
G1
MSB G5
G1
G3
G2
LSB B0
G2
G4
G3
B1
G3
G5
G4
B2
G4
G6
G5
B3
G5
G7
0
B4
GP4
B0
0
MSB B5 GP5
B1
B0
HS
B0
B2
B1
VS
B1
B3
B2
DE
B2
B4
B3
GP0
B3
B5
B4
GP1
B4
B6
B5
GP2
B5
B7
HS
GND
HS
HS
VS
GND
VS
VS
DE
GND
DE
DE
Scenario Scenario Scenario Scenario
4
3
2
1
905 Pin
Name
RO
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
905 Pin
Name
916 Pin
Name
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
916 Pin
Name
24-bit 18-bit 18-bit 18-bit
RGB
RGB
RGB
RGB
R0
GP0 LSB R0
0
R1
GP1
R1
0
R2
R0
R2
R0
R3
R1
R3
R1
R4
R2
R4
R2
R5
R3
MSB R5
R3
R6
R4
LSB G0
R4
R7
R5
G1
R5
G0
GP2
G2
0
G1
GP3
G3
0
G2
G0
G4
G0
G3
G1
MSB G5
G1
G4
G2
LSB0
G2
G5
G3
B1
G3
G6
G4
B2
G4
G7
G5
B3
G5
B0
GP4
B4
0
B1
GP5 MSB B5
0
B2
B0
HS
B0
B3
B1
VS
B1
B4
B2
DE
B2
B5
B3
GP0
B3
B6
B4
GP1
B4
B7
B5
GP2
B5
HS
HS
GND
HS
VS
VS
GND
VS
DE
DE
GND
Scenario Scenario Scenario Scenario
1
2
3
4
Scenario 4
Scenario 4 supports an 18-bit RGB color mapping and 3 em-
bedded video control signals. All LSBs are set to “0”. FRC and
white balance may be enabled with this scenario.
Scenario 3
Scenario 3 supports an 18-bit RGB color mapping, 3 un-em-
bedded video control signals, and up to three general purpose
signals. This scenario is NOT supported when FRC or white
balance are enabled on the DS90UR916.
Scenario 2
Scenario 2 supports an 18-bit RGB color mapping, 3 embed-
ded video control signals, and up to six general purpose
signals. This scenario is NOT supported when FRC or white
balance are enabled on the DS90UR916.
Scenario 1
Scenario 1 supports the 24-bit RGB color mapping, along with
the 3 embedded video control signals. This is the native mode
for the chipset. FRC and white balance may be enabled with
this scenario.
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