DS90UR916Q Datasheet, PDF (20/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

rate setting when driving longer traces or a heavier capacitive
load.
Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal ter-
mination. A capacitor may be placed on this pin for additional
common-mode filtering of the differential pair. This can be
useful in high noise environments for additional noise rejec-
tion capability. A 0.1µF capacitor may be connected to this
pin to Ground.
SSCG Generation — Optional
The Des provides an internally generated spread spectrum
clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI.
Output SSCG deviations to ±2.0% (4% total) at up to 35kHz
modulations nominally are available. See Table 3. This fea-
ture may be controlled by external STRAP pins or by register.
TABLE 3. SSCG Configuration (LF_MODE = L) — Des Output
SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
SSC[3:0] Inputs
LF_MODE = L (20 - 65 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
fdev (%)
Off
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
Result
fmod (kHz)
Off
PCLK/2168
PCLK/1300
PCLK/868
PCLK/650
SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
TABLE 4. SSCG Configuration (LF_MODE = H) — Des Output
SSC[3:0] Inputs
LH_MODE = H (5 - 20 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
fdev (%)
Off
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
Result
fmod (kHz)
Off
PCLK/620
PCLK/370
PCLK/258
PCLK/192
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