DS90UR916Q Datasheet, PDF (19/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

FIGURE 14. Default FRC Algorithm
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Signal Quality Enhancers
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial
stream to increase the eye opening to the Des input. Note this
function cannot be seen at the RxIN+/- input but can be ob-
served at the serial test port (CMLOUTP/N) enabled via the
Serial Bus control registers. The equalization feature may be
controlled by the external pin or by register.
TABLE 2. Receiver Equalization Configuration Table
EQ3
INPUTS
EQ2
EQ1
EQ0
Effect
L
L
L
H
~1.5 dB
L
L
H
H
~3 dB
L
H
L
H
~4.5 dB
L
H
H
H
~6 dB
H
L
L
H
~7.5 dB
H
L
H
H
~9 dB
H
H
L
H
~10.5 dB
H
H
H
H
~12 dB
X
X
X
L
OFF*
* Default Setting is EQ = Off
The quality of the equalized signal may be assessed by mon-
itoring the differential eye opening at the CMLOUTP/N. The
Receiver Differential Input Threshold and Input Jitter Toler-
ance define the acceptable data eye opening. A differential
probe should be used to measure across a 100Ohm termi-
nation resistor between the CMLOUTP/N pins. Figure 15
illustrates the eye opening.
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FIGURE 15. CMLOUT Eye Opening
EMI Reduction Features
Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK)
of the Des feature a selectable output slew. The DATA ((RGB
[7:0], VS, HS, DE) are controlled by strap pin or register bit
OS_DATA. The PCLK is controlled by strap pin or register bit
OS_PCLK. When the OS_PCLK/DATA = HIGH, the maxi-
mum slew rate is selected. When the OS_PCLK/DATA =
LOW, the minimum slew rate is selected. Use the higher slew
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