DS90UR916Q Datasheet, PDF (18/41 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement

FIGURE 13. White Balance LUT Configurations
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Adaptive Hi-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differ-
entiating image quality. It reduces 24-bit RGB (8 bits per sub-
pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color
gradients, and allowing the flexibility to use lower cost 18-bit
displays. FRC (Frame Rate Control) dithering is a method to
emulate “missing” colors on a lower color depth LCD display
by changing the pixel color slightly with every frame. FRC is
achieved by controlling on and off pixels over multiple frames
(Temporal). Static dithering regulates the number of on and
off pixels in a small defined pixel group (Spatial). The FRC
module includes both Temporal and Spatial methods and also
Hi-FRC. Conventional FRC can display only 16,194,277 col-
ors with 6-bit RGB source. “Hi-FRC” enables full (16,777,216)
color on an 18-bit LCD panel. The “adaptive” FRC module
also includes input pixel detection to apply specific Spatial
dithering methods for smoother gray level transitions. When
enabled, the lower LSBs of each RGB output are not active;
only 18 bit data (6 bits per R,G and B) are driven to the display.
This feature is enabled via serial bus register control.
Two FRC functional blocks are available, and may be inde-
pendently enabled. FRC1 precedes the white balance LUT,
and is intended to be used when 24-bit data is being driven
to an 18-bit display with a white balance LUT that is calibrated
for an 18-bit data source. The second FRC block, FRC2, fol-
lows the white balance block and is intended to be used when
fine adjustment of color temperature is required on an 18-bit
color display, or when a 24-bit source drives an 18-bit display
with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user
must provide a description of the display timing control sig-
nals. The timing mode, “sync mode” (HS, VS) or “DE only”
must be specified, along with the active polarity of the timing
control signals. All this information is entered to DS90UR916
control registers via the serial bus interface.
Adaptive Hi-FRC dithering consists of several components.
Initially, the incoming 8-bit data is expanded to 9-bit data. This
allows the effective dithered result to support a total of 16.7
million colors. The incoming 9-bit data is evaluated, and one
of four possible algorithms is selected. The majority of incom-
ing data sequences are supported by the default dithering
algorithm. Certain incoming data patterns (black/white pixel,
full on/off sub-pixel) require special algorithms designed to
eliminate visual artifacts associated with these specific gray
level transitions. Three algorithms are defined to support
these critical transitions.
An example of the default dithering algorithm is illustrated in
Figure 14. The “1” or “0” value shown in the table describes
whether the 6-bit value is increased by 1 (“1”) or left un-
changed (“0”). In this case, the 3 truncated LSBs are “001”.
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