NS32FV16 Datasheet, PDF (79/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

4 0 Device Specifications (Continued)
4 4 2 2 Input Signal Requirements NS32FX161-15 NS32FX164-20 and NS32FX164-25 (Continued)
Symbol Figure Description
Reference
Conditions
NS32FX161-15 NS32FX164-20 NS32FX164-25 _Units
Min Max Min Max Min Max
t_PWR
4-18 Power Stable to After V_CC Reaches 4 5V
RSTI R E
50
40
30
ms
(Note 2)
t_RSTw 4-19 RSTI Pulse Width At 0 8V (Both Edges)
64
64
64
t_CTp
t_INTh
4-16 INT Signal Hold After R E CTTL T2 of
0
0
0
ns
Interrupt Acknowledge Cycle
t_NMIs
4-17 NMI Setup Time Before F E CTTL
15
14
12
ns
t_NMIh
4-17 NMI Hold Time After F E CTTL
0
0
0
ns
t_SPCd
4-12
SPC Pulse Delay After F E CTTL T4
from Slave
(Note 2)
t_SPCs
t_SPCh
t_ADSs
4-12
4-12
4-9
SPC Input Setup
SPC Hold Time
ADS Input Setup
Before R E CTTL
After R E CTTL
Before F E CTTL
te ^tADSh
4-9 ADS Input Hold After F E CTTL T1
(Note 3)
t_DDINs
4-9 DDIN Input Setup Before F E CTTL
t_DDINih 4-9 DDIN Input Hold After R E CTTL T4
Note 1 t_Dih is always less than or equal to t_RDia
Note 2 Not tested guaranteed by design
Obsole ^{Note 3 ADS must be deasserted before state T4 of the DMA controller cycle}
2
2
2
t_CTp
22
21
20
ns
0
0
0
ns
15 t_CTpb3 14 t_CTpb3 12 t_CTpb3 ns
0
0
0
ns
15
14
12
ns
0
0
0
ns
78