NS32FV16 Datasheet, PDF (66/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
3 5 5 6 Special Bus Cycles
cial write cycle and ignores the data placed on the data bus
Special bus cycles are performed during CPU accesses to
the DSP Module (DSPM) registers or internal RAM These
cycles may be used by external logic to track CPU activities
involving on-chip bus transactions
during a special read cycle The 24 least significant address
bits of the DSPM register being accessed are output on the
AD0–AD15 and A16–A23 signals Figure 3-24 shows the
timing for special read and write cycles
A special bus cycle starts with the assertion of the special
3 5 5 7 Slave Processor Bus Cycles
output signal IAS The ALE signal stays high during the en-
A Slave Processor bus cycle always takes exactly two clock
tire cycle and the signals ADS TSO DBE RD and WR are
cycles labeled T1 and T4 (see Figures 3-25 and 3-26 )
not activated CWAIT is ignored
During a Read cycle SPC is active from the beginning of T1
A CPU access to a DSP Module register or internal RAM
occurring while a vector operation is being executed is de-
layed until the end of the vector operation This delay can-
not be observed externally
to the beginning of T4 and the data is sampled at the end of
T1 The Cycle Status pins lead the cycle by one clock peri-
od and are sampled on the leading edge of SPC During a
Write cycle the CPU applies data and activates SPC at T1
removing SPC at T4 The Slave Processor latches the
The CPU drives the data bus with the same data that is
status on the leading edge of SPC and latches data on the
Obsolete ^{being written into the on-chip register or RAM during a spe-}
trailing edge
FIGURE 3-24 Special Bus Cycle Timing
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