NS32FV16 Datasheet, PDF (3/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

Table of Contents
1 0 PRODUCT INTRODUCTION
3 2 2 Returning from an Exception Service
6
Procedure
30
1 1 NS32FX164 Special Features
6
3 2 3 Maskable Interrupts
34
2 0 ARCHITECTURAL DESCRIPTION
7
3 2 3 1 Non-Vectored Mode
34
2 1 Register Set
7
3 2 3 2 Vectored Mode Non-Cascaded
Case
35
2 1 1 General Purpose Registers
7
3 2 3 3 Vectored Mode Cascaded Case
35
2 1 2 Address Registers
8
3 2 4 Non-Maskable Interrupt
37
2 1 3 Processor Status Register
8
2 1 4 Configuration Register
9
3 2 5 Traps
37
2 1 5 DSP Module Registers
9
3 2 6 Priority among Exceptions
37
2 2 Memory Organization
11
3 2 7 Exception Acknowledge Sequences Detailed
Flow
39
2 2 1 Address Mapping
12
2 3 Modular Software Support
12
2 4 Instruction Set
12
2 4 1 General Instruction Format
12
2 4 2 Addressing Modes
14
2 4 3 Instruction Set Summary
16
2 5 Graphics Support
20
te ^{2 5 1 Frame Buffer Addressing}
20
2 5 2 BITBLT Fundamentals
20
2 5 2 1 Frame Buffer Architecture
21
2 5 2 2 Bit Alignment
21
2 5 2 3 Block Boundaries and Destination
Masks
21
2 5 2 4 BITBLT Directions
22
le ^{2 5 2 5 BITBLT Variations}
23
2 5 3 Graphics Support Instructions
23
2 5 3 1 BITBLT (BIT-aligned BLock Transfer) 23
2 5 3 2 Pattern Fill
24
2 5 3 3 Data Compression Expansion and
Magnify
24
o _{2 5 3 3 1 Magnifying Compressed}
Data
26
3 0 FUNCTIONAL DESCRIPTION
26
s _{3 1 Instruction Execution}
26
3 1 1 Operating States
26
3 1 2 Instruction Endings
26
3 1 2 1 Completed Instructions
27
b 3 1 2 2 Suspended Instructions
27
3 1 2 3 Terminated Instructions
27
3 1 2 4 Partially Completed Instructions
27
3 1 3 Slave Processor Instructions
27
3 1 3 1 Slave Processor Protocol
27
O ^{3 1 3 2 Floating-Point Instructions}
28
3 2 7 1 Maskable Non-Maskable Interrupt
Sequence
39
3 2 7 2 SLAVE ILL SVC DVZ FLG BPT UND
Trap Sequence
39
3 2 7 3 Trace Trap Sequence
39
3 3 Debugging Support
40
3 3 1 Instruction Tracing
40
3 4 DSP Module
40
3 4 1 Programming Model
40
3 4 2 RAM Organization and Data Types
41
3 4 2 1 Integer Values
41
3 4 2 2 Aligned-Integer Values
41
3 4 2 3 Real Values
41
3 4 3 4 Aligned-Real Values
41
3 4 2 5 Extended Precision Real Values
41
3 4 2 6 Complex Values
42
3 4 3 Command List Format
42
3 4 4 CPU Core Interface
42
3 4 4 1 Synchronization of Parallel Operation 42
3 4 4 2 DSPM RAM Organization
43
3 4 5 DSPM Instruction Set
43
3 4 5 1 Conventions
43
3 4 5 2 Type Casting
43
3 4 5 3 General Notes
44
3 4 5 4 Load Register Instructions
44
3 4 5 5 Store Register Instructions
45
3 4 5 6 Adjust Register Instructions
46
3 4 5 7 Flow Control Instructions
47
3 4 5 8 Internal Memory Move Instructions 48
3 4 5 9 External Memory Move Instructions 48
3 4 5 10 Arithmetic Logical Instructions
49
3 4 5 11 Multiply-and-Accumulate
Instructions
49
3 2 Exception Processing
29
3 2 1 Exception Acknowledge Sequence
29
3 4 5 12 Multiply-and-Add Instructions
50
3 4 5 13 Clipping and Min Max Instructions 52
3 4 5 14 Special Instructions
53
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