NS32FV16 Datasheet, PDF (69/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
Cycle
Type
Address
TABLE 3-6 Data Access Sequences
HBE
A0
High Bus
A Odd Word Access Sequence
Low Bus
1 Odd Byte A
2 Even Byte A a 1
Byte 1
0
1
Byte 0
1
0
Don’t Care
B Even Double-Word Access Sequence
Byte 0
Don’t Care
Byte 1
wA
Byte 3
Byte 2
Byte 1
Byte 0
wA
1 Even Word A
0
0
Byte 1
Byte 0
1 Even Word A a 2
0
0
Byte 3
Byte 2
C Odd Double-Word Access Sequence
1 Odd Byte A
2 Even Word A a 1
te ^{3 EvenByte Aa3}
Byte 3
0
0
1
Byte 2
1
0
0
Byte 1
Byte 0
Byte 2
Don’t Care
D Even Quad-Word Access Sequence
Byte 0
Don’t Care
Byte 1
Byte 3
wA
Byte 7 Byte 6 Byte 5 Byte 4
1 Even Word A
2 Even Word A a 2
Byte 3
0
0
Byte 2
0
0
Byte 1
Byte 1
Byte 3
Other Bus Cycles (Instruction Prefetch or Slave) can occur here
le ^{3 EvenWord Aa4}
4 Even Word A a 6
0
0
Byte 5
0
0
Byte 7
E Odd Quad-Word Access Sequence
Byte 0
Byte 0
Byte 2
Byte 4
Byte 6
wA
Byte 7
o ₁
2
3
Byte 6
Odd Byte
Even Word
Even Byte
Byte 5
A
Aa1
Aa3
Byte 4
Byte 3
0
0
1
Byte 2
1
0
0
s _{Other Bus Cycles (Instruction Prefetch or Slave) can occur here}
4 Odd Byte A a 4
5 Even Word A a 5
6 Even Byte A a 7
0
1
0
0
1
0
Byte 1
Byte 0
Byte 2
Don’t Care
Byte 4
Byte 6
Don’t Care
Byte 0
Don’t Care
Byte 1
Byte 3
Don’t Care
Byte 5
Byte 7
wA
b _{3 5 5 9 Bus Access Control}
The NS32FX164 CPU has the capability of relinquishing its
control of the bus upon request from a DMA controller or
another CPU This capability is implemented by means of
the HOLD (Hold Request) and HLDA (Hold Acknowledge)
O ^{pins By asserting HOLD low an external device requests}
set AD0 – AD15 A16 – A23 and HBE to the TRI-STATE
condition and has switched ADS and DDIN to the input
mode ALE is asserted in T4 and stays high during the time
the bus is granted The CPU now monitors ADS and DDIN
from the external device to generate the relevant strobe
signals (i e TSO DBE RD or WR) To return control of the
access to the bus On receipt of HLDA from the CPU the
bus to the CPU the device sets HOLD inactive and the
device may perform bus cycles as the CPU at this point has
CPU acknowledges it by setting HLDA inactive
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