NS32FV16 Datasheet, PDF (38/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
3 2 4 Non-Maskable Interrupt
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin The CPU performs an
‘‘Interrupt Acknowledge’’ bus cycle from Address FFFF00₁₆
when processing of this interrupt actually begins The vector
value used for the Non-Maskable Interrupt is taken as 1
regardless of the value read from the bus
The service procedure returns from the Non-Maskable-In-
terrupt using the Return from Trap (RETT) instruction No
special bus cycles occur on return
3 2 5 Traps
Traps are processing exceptions that are generated as di-
rect results of the execution of an instruction
Trap (FLG) The FLAG instruction detected a ‘‘1’’ in the
PSR F-bit
Trap (BPT) The Breakpoint (BPT) instruction was execut-
ed
Trap (TRC) The instruction just completed is being traced
Refer to Section 3 3 1 for details
Trap (UND) An undefined opcode was encountered by the
CPU
3 2 6 Priority among Exceptions
The CPU checks for specific exceptions at various points
while executing an instruction It is possible that several ex-
ceptions occur simultaneously In that event the CPU re-
sponds to the exception with highest priority
The return address saved on the stack by any trap except
Figure 3-11 shows an exception processing flowchart
Trap (TRC) is the address of the first byte of the instruction
during which the trap occurred
When a trap is recognized maskable interrupts are not dis-
abled
There are 8 trap conditions recognized by the NS32FX164
as described below
Trap (SLAVE) An exceptional condition was detected by
the Floating-Point Unit during the execution of a Slave In-
te ^{struction This trap is requested via the Status Word re-}
turned as part of the Slave Processor Protocol (Section
3 1 3 1)
Trap (ILL) Illegal operation A privileged operation was at-
tempted while the CPU was in User Mode (PSR bit U e 1)
Trap (SVC) The Supervisor Call (SVC) instruction was exe-
cuted
le ^{Trap (DVZ) An attempt was made to divide an integer by}
zero (The FPU trap is used for Floating-Point division by
Obso ^zero)
Before executing an instruction the CPU checks for pend-
ing interrupts or Trap (TRC) The CPU responds to any
pending interrupt requests nonmaskable interrupts are rec-
ognized with higher priority than maskable interrupts If no
interrupts are pending then the CPU checks the P-flag in
the PSR to determine whether a Trap (TRC) is pending If
the P-flag is 1 a Trap (TRC) is processed If no interrupt or
Trap (TRC) is pending the CPU begins executing the in-
struction
While executing an instruction the CPU may recognize up
to two exceptions
1 Interrupt if the instruction is interruptible
2 One of 7 mutually exclusive traps SLAVE ILL SVC
DVZ FLG BPT UND
If no exception is detected while the instruction is executing
then the instruction is completed and the PC is updated to
point to the next instruction
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