NS32FV16 Datasheet, PDF (78/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

4 0 Device Specifications (Continued)
4 4 2 Timing Tables (Continued)
4 4 2 1 Output Signals Internal Propagation Delays NS32FX161-15 NS32FX164-20 NS32FX164-25
Symbol Figure
Description
Reference
Conditions
NS32FX161-15
Min
Max
NS32FX164-20
Min
Max
NS32FX164-25
Units
Min
Max
t_IASa
t_IASia
4-6 IAS Signal Active
4-6 IAS Signal Inactive
(Note 4)
After R E CTTL T1
14
13
12
ns
After R E CTTL T1 0 5 t_CTp 0 5 t_CTp 0 5 t_CTp 0 5 t_CTp 0 5 t_CTp 0 5 t_CTp
b6 ns a16 ns b6 ns a15 ns b6 ns a14 ns
t_IASw
4-6 IAS Pulse Width
At 0 8V (Both Edges) 20
15
10
ns
t_AIASs
4-6 AD0–AD15 Setup Before IAS T E
10
10
10
ns
t_ILOa
4-14 ILO Signal Active
After R E CTTL
14
13
12
ns
t_ILOia
4-14 ILO Signal Inactive After R E CTTL
14
13
12
ns
t_RSTOa 4-19 RSTO Signal Active After R E CTTL
14
13
12
ns
t_RSTOia 4-19 RSTO Signal Inactive After R E CTTL
14
13
12
ns
t_RTOI
4-19 Reset to Idle
After F E of RSTO
10
(Note 3)
10
10
t_CTp
t_IOUTv 4-20 IOUT Signal Valid After R E CTTL
14
13
12
ns
te ^{tIOUTh 4-20 IOUT Signal Hold}
After R E CTTL
0
0
0
ns
Note 1 Every memory cycle starts with T4 during which Cycle Status is applied If the CPU was idling the sequence will be ‘‘ Ti T4 T1 ’’ If the CPU was
not idling the sequence will be ‘‘ T4 T1 ’’
Note 2 The parameters related to the ‘‘floating not floating’’ conditions are guaranteed by characterization Due to tester conditions these parameters are not
100% tested
Note 3 Not tested guaranteed by design
Note 4 Minimum values not tested guaranteed by design
Note 5 When the load on AD0–15 is increased to 90 pF the value of t_ALv is increased by no more than 5 ns When the load on A16–23 is increased to 90 pF the
le ^{value of tAHv is increased by no more than 5 ns}
4 4 2 2 Input Signal Requirements NS32FX164-15 NS32FX164-20 and NS32FX164-25
Symbol Figure
Description
Reference
Conditions
NS32FX164-15
Min Max
o ^tXp
4-15 OSCIN Clock Period R E OSCIN
33
500
to Next R E OSCIN
t_Xh
4-15 OSCIN High Time At 3 5V (Both Edges) 0 5 t_Xp
(External Clock)
b 5 ns
s _tXI
4-15 OSCIN Low Time At 1 0V (Both Edges) 0 5 t_Xp
b 5 ns
t_DIs
4-4 4-11 Data In Setup
t_DIh
4-4 4-11 Data In Hold
b _{(Note 1)}
Before R E CTTL T4 15
After R E CTTL T4
0
t_CWs
4-4 4-5 CWAIT Signal Setup Before R E CTTL
T3 or T3(w)
18
O ^tCWh
4-4 4-5 CWAIT Signal Hold After R E CTTL
T3 or T3(w)
0
NS32FX164-20
Min Max
25
500
0 5 t_Xp
b 4 ns
0 5 t_Xp
b 4 ns
14
0
13
0
NS32FX164-25
Min Max
20
500
0 5 t_Xp
b 3 ns
0 5 t_Xp
b 3 ns
10
0
10
0
Units
ns
ns
ns
ns
ns
t_HLDs
4-7 4-8 HOLD Setup Time
Before R E CTTL
T2 or Ti
16
15
14
ns
t_HLDh
4-7 4-8 HOLD Hold Time
After R E CTTL Ti
0
0
0
ns
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