NS32FV16 Datasheet, PDF (64/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
bsolete FIGURE3-23 CycleExtensionofaReadCycle
TL EE 11267 – 35
3 5 5 4 Instruction Fetch Cycles
Instructions for the NS32FX164 CPU are ‘‘prefetched’’ that
is they are input before being needed into the next available
entry of the eight-byte instruction Queue The CPU performs
O ^{two types of instruction Fetch cycles Sequential and Non-}
A Non-Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program Any jump or
branch instruction a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential In addition
certain instructions flush the instruction queue causing the
Sequential These can be distinguished from each other by
next instruction fetch to display Non-Sequential status Only
their differing status combinations on pins ST0–ST3 (Sec-
the first bus cycle after a break displays Non-Sequential
tion 3 5 5 1)
status and that cycle is either an Even Word Read or an
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Odd Byte Read depending on whether the distination ad-
dress is even or odd
Queue is not currently full Sequential Fetches are always
Even Word Read cycles (Table 3-5)
63