NS32FV16 Datasheet, PDF (72/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
3 5 5 10 Instruction Status
In addition to the four bits of Bus Cycle status (ST0 – 3) the
NS32FX164 CPU also presents Instruction Status informa-
tion on three separate pins These pins differ from
ST0 – 3 in that they are synchronous to the CPU’s internal
instruction execution section rather than to its bus interface
INT
Interrupt
A low level on this pin requests a maskable inter-
rupt INT must be kept asserted until the interrupt
is acknowledged
NMI
Non-Maskable Interrupt
A High-to-Low transition on this signal requests a
non-maskable interrupt
section
PFS (Program Flow Status) is pulsed low as each instruction
begins execution It is intended for debugging purposes
CWAIT
Note INT and NMI are true asynchronous inputs Therefore
no external synchronizing circuit is needed
Continuous Wait
U S originates from the U-bit of the Processor Status Regis-
ter and indicates whether the CPU is currently running in
User or Supervisor mode Although it is not synchronous to
Causes the CPU to insert continuous wait states
if sampled low at the end of T2 and each follow-
ing T-State See Section 3 5 5 3
bus cycles there are guarantees on its validity during any
OSCIN Crystal External Clock Input
given bus cycle See the Timing Specifications in Section
Input from a crystal or an external clock source
442
See Section 3 5 2
ILO (Interlocked Operation) is activated during an SBITI (Set
Bit Interlocked) or CBITI (Clear Bit Interlocked) instruction
It is made available to external bus arbitration circuitry in
order to allow these instructions to implement the sema-
phore primitive operations for multi-processor communica-
tion and resource sharing ILO is guaranteed to be active
during the operand accesses performed by the interlocked
instructions
4 0 Device Specifications te Note The acknowledge of HOLD is on a cycle by cycle basis Therefore it
is possible to have HLDA active when an interlock operation is in
progress In this case ILO remains low and the interlocked instruction
continues only after HOLD is de-asserted
4 1 NS32FX164 PIN DESCRIPTIONS
The following is a brief description of all NS32FX164 pins
le ^{The descriptions reference portions of the Functional De-}
scription Section 3 0
Note An asterisk next to the signal name indicates a TRI-STATE condition
for that signal during HOLD acknowledge
4 1 1 Supplies
V_CC
Power
o a5V positive supply
GND
Ground
Ground reference for both on-chip logic and
output drivers
s _{4 1 2 Input Signals}
RSTI Reset Input
Schmitt triggered asynchronous signal used to
generate a CPU reset See Section 3 5 4
b Note The reset signal is a true asynchronous input Therefore
no external synchronizing circuit is needed
HOLD Hold Request
When active causes the CPU to release the bus
for DMA or multiprocessing purposes See Sec-
O^{tion 3559}
4 1 3 Output Signals
A16 – A23 High-Order Address Bits
These are the most significant 8 bits of the mem-
ory address bus
HBE
High Byte Enable
Status signal used to enable data transfers on
the most significant byte of the data bus
ST0 – 3 Status
Bus cycle status code ST0 is the least signifi-
cant Encodings are
0000 Idle CPU Inactive on Bus
0001 Idle WAIT Instruction
0010 DSP Module Data Transfer
0011 Idle Waiting for Slave
0100 Interrupt Acknowledge Master
0101 Interrupt Acknowledge Cascaded
0110 End of Interrupt Master
0111 End of Interrupt Cascaded
1000 Sequential Instruction Fetch
1001 Non-Sequential Instruction Fetch
1010 Data Transfer
1011 Read Read-Modify-Write Operand
1100 Read for Effective Address
1101 Transfer Slave Operand
1110 Read Slave Status Word
1111 Broadcast Slave ID
US
User Supervisor
User or Supervisor Mode status High indicates
User Mode low indicates Supervisor Mode
ILO
Interlocked Operation
When active indicates that an interlocked opera-
tion is being executed
HLDA Hold Acknowledge
Activated by the CPU in response to the HOLD
Note If the HOLD signal is generated asynchronously its set
input to indicate that the CPU has released the
up and hold times may be violated In this case it is
recommended to synchronize it with CTTL to minimize
the possibility of metastable states
bus
PFS
Program Flow Status
The CPU provides only one synchronization stage to
A pulse on this signal indicates the beginning of
minimize the HLDA latency This is to avoid speed deg-
execution of an instruction
radations in cases of heavy HOLD activity (i e DMA
controller cycles interleaved with CPU cycles)
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