NS32FV16 Datasheet, PDF (76/104 Pages) Texas Instruments – Advanced Imaging/Communication Signal Processors

4 0 Device Specifications (Continued)
4 4 2 Timing Tables
4 4 2 1 Output Signals Internal Propagation Delays NS32FX161-15 NS32FX164-20 NS32FX164-25
 The output to input timings (e g address to data-in) are at least 2 ns better than the worst case values calculated from the
output valid and input setup times relative to CTTL
Symbol Figure
Description
Reference
Conditions
NS32FX161-15
Min Max
NS32FX164-20
Min Max
NS32FX164-25
Units
Min Max
t_CTp
4-15 CTTL Clock Period
R E CTTL to Next
R E CTTL
66
1000
50
1000
40
1000 ns
t_CTh
4-15 CTTL High Time
At 2 0V (Both Edges)
0 5 t_CTp
b 6 ns
0 5 t_CTp
b 5 ns
0 5 t_CTp
b 5 ns
t_CTI
4-15 CTTL Low Time
At 0 8V (Both Edges)
0 5 t_CTp
b 6 ns
0 5 t_CTp
b 5 ns
0 5 t_CTp
b 4 ns
t_CTr
t_CTf
t_XCTd
t_XFr
t_FCr
t_FCf
t_ALv
t_ALh
t_AHv
t_AHh
t_ALfr
t_ALf
t_AHf
t_Dv
t_Dh
t_ADSa
t_ADSia
t_ADSw
t_ADSf
t_ALADSs
t_HBEv
t_HBEh
4-15
4-15
4-15
4-15
4-15
4-15
4-4
4-4
4-4
4-4
4-4
4-7
4-7
4-5
4-5
4-4
4-4
4-5
4-7
4-4
4-4
4-4
CTTL Rise Time
0 8V to 2 0V
on R E CTTL
6
5
4
ns
CTTL Fall Time
2 0V to 0 8V
on F E CTTL
6
5
4
ns
OSCIN to CTTL Delay 4 2V on R E
OSCIN to R E CTTL
29
29
25 ns
OSCIN to FCLK
R E Delay
4 2V on R E OSCIN
to R E FCLK
25
20
15 ns
FCLK to CTTL
te ^{RE Delay}
R E FCLK to R E CTTL
10
10
10 ns
FCLK to CTTL
F E Delay
R E FCLK to F E CTTL
10
10
10 ns
AD0–AD15 Valid
(Note 5)
After R E CTTL T1
14
13
12 ns
AD0–AD15 Hold
After R E CTTL T2
0
0
0
ns
A16–A23 Valid
le ^(Note5)
After R E CTTL T1
14
13
12 ns
A16–A23 Hold
After R E CTTL
Next T1 or Ti
0
0
0
ns
AD0–AD15 Floating After R E CTTL T2
(during Read)
14
13
12 ns
AD0–AD15 Floating After R E CTTL Ti
14
13
12 ns
o _{A16–A23 Floating}
After R E CTTL Ti
14
13
12 ns
Data Valid (Write Cycle) After R E CTTL
T2 or T1
14
13
12 ns
s ^{Data Hold}
After R E CTTL
Next T1 or Ti
0
0
0
ns
ADS Signal Active
After R E CTTL T1
14
13
12 ns
ADS Signal Inactive
(Note 4)
After R E CTTL T1
0 5 t_CTp 0 5 t_CTp 0 5 t_CTp 0 5 t_CTp 0 5 t_CTp 0 5 t_CTp
b6 ns a16 ns b6 ns a15 ns b6 ns a14 ns
b ADS Pulse Width
At 0 8V (Both Edges)
20
15
10
ns
ADS Floating
After R E CTTL Ti
14
13
12 ns
AD0–AD15 Setup
Before ADS T E
10
10
10
ns
HBE Signal Valid
After R E CTTL T1
14
13
12 ns
O^{HBE Signal Hold}
After R E CTTL
Next T1 or Ti
0
0
0
ns
t_HBEf
4-7 HBE Signal Floating After R E CTTL Ti
14
13
12 ns
75