GC5316_14 Datasheet, PDF (72/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
www.ti.com
7.6 AC Characteristics
PARAMETER
MIN MAX UNIT
FCK
FCK
Clock frequency (adcclk, rxclk, txclk) in selected modes(6)(9)
Clock frequency (adcclk, rxclk, txclk) unrestricted(6)
125 MHz
80
MHz
tADCKL
tRXCKL
tTXCKL
Clock low period (below VIL) (adcclk, rxclk, txclk)(6)
3
ns
tADCKH
tRXCKH
tTXCKH
tr, tf
tsu(TX)
tsu(RX)
tsu(RXB)
tsu(AD)
th(TX)
th(RX)
th(RXB)
th(AD)
td(TX)
td(RX)
tOH(TX)
tOH(RX)
FJCK
tJCKL
tJCKH
tsu(J)
th(J)
td(J)
tsu(UPA)
th(UPA)
tsu(UPD)
th(UPD)
th
td(UP)
tUPCKL
tUPCKH
Clock high period (above VIH) (adcclk, rxclk, txclk)(6)
Clock rise and fall times (VIL to VIH) (adcclk, rxclk, txclk)(8)
Input setup (txin_[0−11]_[a−b], tx_sync[a−d]) before txclk rises(6)
Input setup (rx_sync[a−d]) before rxclk rises(6)
Input setup (rxin_[a−d]_[0−15]) before rxclk rises adc_fifo bypassed(6)
Input setup (rxin[a−d]_[0−15]) before adcclk rises adc_fifo active(6)
Input hold (txin_[0−11]_[a−b], tx_sync[a−d]) after txclk rises(6)
Input hold (rx_sync[a−d]) after rxclk rises(6)
Input hold (rxin[a−d]_[0−15]) after rxclk rises adc_fifo bypassed(6)
Input hold (rxin[a−d]_[0−15]) after adcclk rises adc_fifo active(6)
Data output delay (tx_sync_out_[0−5], tx_iflag, txout_[a−d]_[0−17]) after txclk rises(6)
Data output delay (rx_sync_out_[0−5], rxout_[0−11] _[a−d]) after rxclk rises(6)
Data output hold (tx_sync_out_[0−5], tx_iflag, txout_[a−d]_[0−17]) after txclk rises(6)
Data output hold (rx_sync_out_[0−5], rxout_[0−11] _[a−d]) after rxclk rises(6)
JTAG clock frequency (tck)(6)
JTAG clock low period (below VIL) (tck)(6)
JTAG clock high period (above VIH) (tck)(6)
JTAG input (tdi or tms) setup before tck goes high(6)
JTAG input (tdi or tms) hold time after tck goes high(6)
JTAG output (tdo) delay from falling edge of tck(6)
Microprocessor address setup to falling edge of controls(6)
Microprocessor address hold from rising edge of controls(6)
Microprocessor data setup to rising edge of controls during writes(6)
Microprocessor data hold from rising edge of controls during writes(6)
Microprocessor data output hold from rising edge of controls (read)(7)
Microprocessor data output delay from falling edge of controls (read)(6)
Microprocessor control low time(6)
Microprocessor control high time(6)
3
2
2.2
2.5
0.4
2.2
1.1
0.5
3.5
1
6.5
6.5
1.5
1.5
40
8
8
2
9
6
2.5
2
12
2.6
0
36
30
8.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: _{Timing is measured from the respective clock at VPAD /2 to input or output at VPAD /2. Output loading is a 50-Ω transmission line whose delay is}
calibrated out.
(6) _{Each part is tested at 90°C case temperature for the given specification. Lots are sample tested at −40°C.}
(7) _{Controlled by design and process and not directly tested. Verified on initial part evaluation.}
(8) _{Recommended practice.}
(9) _{Excluding rx_sync_out , rx_sync_out_[1−5], tx_sync_out, tx_sync_out_[1−5]. Resampler active or adcclk < 80 MHz.}
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