GC5316_14 Datasheet, PDF (14/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
2.3.5 Receive CIC Filter
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S hift
18
Z ^−1
Z ^−1
Z ^−1
Z ^−1
Down
Z ^−1
Z ^−1
54
shift
5−36
24
N
D ecim ate
by 4−32
Z ^−m1
Z ^−m2
Z ^−m3
Z ^−m4
Z ^−m5
m1, m2, m3, m4, m5, m6 = 1 or 2
Figure 13. Six Stage CIC Filter
Z ^−m6
24 ^Round 18
&
L imit
The CIC filter provides the first stage of filtering and large-value decimation. The filter consists of six stages and
decimates over a range from 4 to 32.
I data and Q data are handled separately with two CIC filters. In addition, when in CDMA mode (two CDMA channels
processed within a single DDC), another pair of CIC filters handles the B-side channel.
The filter response is (Sin(x)/x)⁶ in character where the key attribute is that the resulting response nulls alias back
to dc when the signal is decimated. The aliasing rejection achieved depends on the bandwidth of the signal of interest
relative to the CIC output sample rate. A good rule of thumb is the signal of interest should be less than 25% of the
CIC output rate. This means that the CIC decimation value should be chosen so that the signal exiting the CIC filter
is oversampled by at least a factor of four. (Generally, it is close enough for digital signals that the CIC output rate
be at least four times the symbol rate).
The filter is equivalent to six stages of a FIR filter with uniform coefficients (six combined boxcar filter stages). Each
filter would be of length Ncic if m=1, or 2×Ncic if m=2.
The filter is made up of six banks of 54-bit accumulator sections followed by six banks of 24-bit subtractor sections.
Each of the subtractor sections can be independently programmed with a differential delay of either one or two. A
shift block follows the last integration stage and can shift the 54 bit accumulated data down by 36−cic_scale (a
programmable factor from 0 to 31 bits).
The CIC filter exhibits a droop across its frequency response. This should be compensated in either the CFIR or PFIR
filters that follow. Typically, droop compensation is done in the CFIR but it is also possible to compensate for CIC
droop in the PFIR filter.
The gain of the receive CIC filter is: Ncic⁶ × 2^{(number of stages where M=2)} × 2^{(−36+CIC_SCALE)} where CIC_SCALE is 0 to
31. There is no rollover protection internal to the CIC or at the final round so the user must guarantee no sample
exceeds full scale prior to rounding. For practical purposes, this means the CIC gain must be less than or equal to
one.
A fixed gain of 12 dB at the output of the CIC can also be programmed.
The post CIC gain is rollover protected. Post CIC gain = 2^{(cic_gain_ddc x 2)}.
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