GC5316_14 Datasheet, PDF (60/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
pser_recv_8pin
D 0120
5
pser_recv_alt
D 0120
5
pser_recv_fsdel
ddcmux_sel_a
ddcmux_sel_b
gain_mon
D 0120
5
U 0120
6
U 0120
6
D 0120
6
rnd_disable
ch_rate_sel
D 0120
6
U 0120
6
remix_only
cic_bypass
U 0120
6
D 0120
6
double_tap
D 0120
6
ssel_cic
U 0120
0B
7
1
6
1
0
2
12
4
4
4
10
1
11
1
8
2
3
1
2
1
0
2
12
3
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0
When set, four pins are used for I and
four pins for Q in UMTS mode. When
cleared, two pins are used for I and two pins
for Q. This is used in combination with the
pser_recv_alt bit. When this bit is set, it
would be set in two adjacent DDC channels;
one would also set the pser_recv_alt bit.
This causes the I channel to be serialized on
four pins and the Q channel to be serialized
on the adjacent channels four pins.
0
When set, this channel’s receive serial
interface outputs the Q data from the
adjacent DDC channel. (set to 0 for even
DDC and to 1 for ODD DDC)
1
Delay between the receive frame sync
output and the MSB of serial data {3, 2, 1, 0}.
0
Controls which samples go to the mixer for
I/Q. (for CDMA channel A or UMTS
channel).
0
Controls which samples go to the mixer for
I/Q. (for CDMA channel B).
0
Combines the gain with the I/Q output
signals when asserted. Look at the AGC
description for more info about the status
bits.
1
Turns off rounding at the AGC output if set.
Normal AGC output otherwise.
0
Tells the DDC what the input clock rate for
the channel is. 0 − rxclk, 1 – rxclk/2, 2 –
rxclk/4, 3 – rxclk/8. For example, if the
resampler_ena =1, the output of the
resampler block is at rxclk/2 rate. So
ch_rate_sel should be set to 1.
0
Assert this when only real input is available
at the DDC’s mixer inputs. This bit holds the
Q portion of the signal to 0.
0
(TESTING PURPOSES) If asserted then the
data from the rxin_a and rxin_b are fed
directly into the cfir input as I and Q
respectively. rxin_a(0) also functions as the
sync_cfir signal and should rise at the
beginning of input data.
0
Set to 0 for normal mode. In double tap
mode, data out of the last PFIR ram in the
main DDC (even numbered DDC) is sent to
the adjacent secondary DDC (odd numbered
DDC) PFIR as input thus forming a 128-tap
delay line. Also data received from the
secondary PFIR summers is added into the
Main DDC’s PFIR sum to form the output.
This enables using a PFIR of length up to
128 instead of 64 as in the normal mode.
When using double tap mode, set
double_tap to 2 for the main (even) DDC and
to 1 for the secondary (odd) DDC.
0
Selects the sync source for the DDC CIC
filter decimation moment. No effect for DUC.
60