GC5316_14 Datasheet, PDF (5/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

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GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
Next the signal is sent to an 8-stage FIFO. This allows an arbitrary phase relationship between adcclk and rxclk. The
frequency relationship is fixed by the configuration. The FIFO can be bypassed, clocking the input data directly on
rxclk. Note that if the FIFO is bypassed, the hold times are longer than usual. If the input rate is a fraction (1/2, 1/4,
or 1/8) of rxclk then ssel_rxin determines which of the multiple rising clock edges are used to sample the data.
Table 1. Programming
VARIABLE
rduz_sens_ena
nz_pwr_mask
adc_fifo_bypass
DESCRIPTION
When enabled adds noise to the ADC input using nz_pwr_mask.
Selects the noise bits to be added to the ADC input sample when rduz_sens_ena is one.
When asserted bypasses the input FIFO. Data is latched directly using the rxclk input when FIFO is
bypassed. Should set this to 0 when input data is to be latched using the adcclk input. Most applications
should not bypass the fifo.
2.1.2 Resampler Block
Two of the four 16-bit data input ports, rxin_a, and rxin_c have resampler blocks. The data is clocked from an external
clock signal adcclk. The real input signal is downconverted by adcclk/4 and is then low-pass filtered and decimated.
Decimation can be either by 1.5 or by 2. Both these decimation modes support up to 24 CDMA DDC channels, or
12 UMTS DDC channels.
Resam p ler D ecim ate by 1.5
adcclk
4
a dcclk
rxclk
=
3
4
rxin_a (or c)
at adcclk
16 _I
Q
18 _I
2
LPF
24 tap
3 ¹⁸ _Q
Figure 3. Resampler Decimate by 1.5 Mode
rx_distribution
bus b (or d)
bus a (or c)
at rxclk/2
The decimate by 1.5 mode requires the input data rate to be 3/4 of the receive clock rate (adcclk frequency is 3/4
rxclk frequency). A 24-tap low-pass decimation filter with programmable 18-bit coefficients removes alias images that
would fold into the passband prior to decimation. The following table shows the performance of filters designed for
various bandwidths when the resampler is decimating by 1.5. The table also shows the resulting passband
frequencies assuming the input data rate is 92.16 MSPS. Each horizontal row is a unique 24-tap filter which is
available on the web.
Table 2. Resampler Filter Performance in the Decimate by 1.5 Mode
GENERAL APPLICATION
PASSBAND
of clk
0.05
0.06
0.07
0.08
0.09
0.1
0.11
0.05
0.06
RIPPLE
dB
0
0
0
0.01
0.03
0.07
0.18
0
0
STOPBAND
dB
−101.5
−98
−91.7
−84.1
−75.6
−67.1
−59.5
−101.5
−98
EXAMPLE APPLICATION
adclk: 92.16 MHz
BANDWIDTH F LOWER F CENTER
MHz
MHz
MHz
18.4
13.8
23
22.1
12
23
25.8
10.1
23
29.5
8.3
23
33.2
6.5
23
36.9
4.6
23
40.6
2.8
23
18.4
13.8
23
22.1
12
23
F UPPER
MHz
32.3
34.1
35.9
37.8
39.6
41.5
43.3
32.3
34.1
5