GC5316_14 Datasheet, PDF (44/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
www.ti.com
Table 18. Programming
VARIABLE
DESCRIPTION
comp_pmeterX_result_lsb(15:0)
Lower 16 bits of the composite power measurement for sum chain X. X= 0, 1, 2, or 3
comp_pmeterX_result_msb(31:16) Upper 16 bits of the composite power measurement for sum chain X. X= 0, 1, 2, or 3
comp_pmeterX_integration_lsb(15:0) Lower 16 bits of the 21-bit integration period. X = 0, 1, 2, or 3
comp_pmeterX_integration_msb(20:16) Upper 5 bits of the 21-bit integration period. X = 0, 1, 2, or 3
comp_pmeterX_sync_delay(8:0)
Power meter delay sync period. X = 0, 1, 2, or 3
comp_pmeterX_interval_lsb(15:0) Lower 16 bits of the 21-bit measurement interval. X = 0, 1, 2, or 3
comp_pmeterX_interval_msb(20:16) Upper 5 bits of the 21-bit measurement interval. The Interval time must be greater than
the integration time for each of the four composite power meters. X = 0, 1, 2, or 3
ssel_comp_pmeter_X(2:0)
Sync source. X = 0, 1, 2, or 3
3.3 GC5316 Transmit Output Interface
18
I
Sum Chain 0
18
Q
18 _{txout_a}
I
Sum Chain 1
Q
txout _ b
I
Sum Chain 2
Q
txout _ c
I
Sum Chain 3
Q
txout _ d
Format ²
txc lk_ out
tx_i_flag
Figure 38. Transmit Output Interface
The GC5316 provides four transmit output signal data ports. Each port can be enabled or disabled. Disabled ports
are held low and can also be tri-stated.
Each 18-bit port outputs the sum of the carriers contributing to the composite signal stack. Output data can be real
or complex valued. Complex I/Q data can be output either interleaved over a single output port, or, over two ports
separately.
Real output data would generally be selected driving a single D/A converter to an IF frequency. Complex output data
would be selected when subsequent post-processing such as power amplifier predistortion is employed. Complex
outputs can also be used to drive a pair of D/A converters (one for I, the other for Q) for direct I/Q upconversion using
a quadrature modulator device.
I and Q complex output data can be interleaved over a single 18-bit port, or, simultaneously over two separate output
ports at half the rate. Signal tx_I_flag is active when I data is being output when in complex output interleaved mode.
When complex output data is noninterleaved, I data is output on port 0 and Q data is output on port 1 for sum chain 0.
For sum chain 1, I data is output on port 2 and Q data is output on port 3.
Real output data is output over a single 18-bit port. For CDMA mode, the maximum real output rate is txclk/2. The
maximum real output rate for UMTS mode is txclk.
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