GC5316_14 Datasheet, PDF (19/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

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GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
For CDMA mode, the integration time is slightly longer. The power read in CDMA mode with a dc input is:
A power: [ I²(X x 4 + 1) + Q²(X x 4 + 0) ]2^−23 Note that one Q sample is missing from the integration.
B power: [ I²(X x 4 + 1) + Q²(X x 4 + 1) ]2^−23
Where X is the integration count.
Table 17. Programming
FIELD
pmeter_result_a_lsb(15:0)
pmeter_result_a_msb (31:16)
pmeter_result_b_lsb (15:0)
pmeter_result_b_msb (31:16)
pmeter_integration_ddc(15:0)
pmeter_sync_delay_ddc(7:0)
pmeter_interval_ddc(7:0)
ssel_pmeter(2:0)
pmeter_sync_disable
DESCRIPTION
Lower 16 bits of the A DDC channel power measurement result.
Upper 16 bits of the A DDC channel power measurement result.
Lower 16 bits of the B DDC channel power measurement result. Only available for CDMA.
Upper 16 bits of the B DDC channel power measurement result. Only available for CDMA.
Integration time = 4(1+pmeter_count_ddc).
Start delay from sync = 3 + pmeter_sync_delay_ddc.
Interval time = 1024(pmeter_interval_ddc+1). Interval time must be greater than (not equal) integration time.
Sync source options
Turns off the sync to the channel power meter. This can be used to individually turn off syncs to a channels
power meter, while still having syncs to other power meters on the chip.
2.5 Receive Gain and AGC
The receive AGC can be used as a simple gain or as a flexible AGC.
2.5.1 Receive Simple Gain
The receive AGC can be used as simple gain by freezing the AGC accumulator at its current level, then clearing the
current value. This is done by setting the agc_clear and agc_freeze bits. The output can be rounded from 3 to 18 bits
using agc_rnd or the full 25 bits can be output by setting agc_rnd_disable.
2.5.2 Receive AGC
Valid
Delay
Delay
Valid
18
Input
Round
4
18 data +
25 7 overflow
Round
18
Output (up to 25 bits in AGC bypass mode)
7 integer &
12 F ractional
19
Ga in
7 integer &
12 Fractional
Threshold
8
Zero Mask Ucnt Ocnt
4
8
8
Dblw Dabv Dzro Dsat
4 44 4
8
Magnitude
Compare
2
Under/Over ²
Detect
5
Shift Select
Valid
19
7 integer & 12 F ractional
Fre eze
Shift
S= +−1, D= 4bit shift
Ucnt Ocnt
16
16
24
24
Accumulate
Limit
A(t) = gain adjust
19
Under Limit
Over Limit
Clear
Figure 16. AGC Block Diagram
19