GC5316_14 Datasheet, PDF (30/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
3.1.3 Transmit UMTS Pilot Code Insertion
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17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Up per R egister Load
18
I State
IÕ
O utp ut
16
I
Logic
IÕ QÕ I Q
0 0 −G G
0 1 GG
QÕ
1 0 −G −G
1 1 G −G
16
Q
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Lower R egister Load (always loaded with all 1s)
G ^{16 A}
(Gain)
R eg
Negate
Synchronization
16-Bit Counter for
Gain Negation
S ync
Sync D elay Counter
16 Bits
(in samples)
16
De la y
Figure 25. Pilot Code Insertion Logic
The pilot code insertion block is used to generate UMTS pilot scrambling sequences and does not apply when
transmitting CDMA. The pilot sequence is summed with the UMTS input baseband data prior to PFIR filtering.
The sequence is complex and generated from two 18-bit shift registers, each with a unique set of feedback taps.
Specific taps are exclusive/or combined to form the I and Q streams. The streams are then modified by a
user-programmed complex gain value. The gain word G is a signed 16-bit value. The output sequence is +− G. Setting
gain to zero turns off pilot insertion.
Note: Gain MUST be set to zero for CDMA operation.
The upper 18-bit shift register is programmed with a starting sequence based on the desired primary scrambling code
(PSC). There are 512 start sequences for all of the BTS codes. The lower register is always started with a string of
all 1s.
When diversity channels are employed, a counter in the synchronization block toggles the sign of the gain value in
a prescribed fashion. The UMTS frame starts with positive gain for 256 chips, then toggles to negative gain for 512
chips, then toggles again to positive gain for 512 chips, etc. until the end of the frame. The last 256 chips of the frame
will be negative gain. This sequence repeats for subsequent frames.
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