GC5316_14 Datasheet, PDF (3/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

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2 GC5316 Receive
GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
16
rxin_a
16
rxin_b
16
rxin_c
16
rxin_d
addcclk
rxclk
(receive chip clock)
rx_distribution
DDC0
2CDMA2000−1X
or 1 UMTS
Frame Sync DDC 0 & 1
DDC1
2CDMA2000−1X
or 1 UMTS
DDCs 2 through 9
DDC10
2CDMA2000−1X
or 1 UMTS
Frame Sync DDC 10 & 11
DDC11
2CDMA2000−1X
or 1 UMTS
Receive
input sync
rx_synca
rx_syncb
rx_syncc
rx_syncd
Receive Syncs
rxout_0_a
rxout_0_b
rxout_0_c
rxout_0_d
Serial Outputs
For CDMA
For UMTS
I CDMA Ch A
I CDMA Ch B
Q CDMA Ch A
Q CDMA Ch B
Imsb UMTS
Imsb−1 UMTS
Qmsb UMTS
Qmsb−1 UMTS
rx_sync_out_0
rxout_1_a
rxout_1_b
rxout_1_c
rxout_1_d
rxout_10_a
rxout_10_b
rxout_10_c
rxout_10_d
rx_sync_out_5
rxout_11_a
rxout_11_b
rxout_11_c
rxout_11_d
rx_sync_out General purpose
output sync
Figure 1. Receive Section
The receive section of the GC5316 consists of the receive input interface, the rx_distribution bus, and 12 digital
downconverter blocks.
The purpose of the receive input interface is to accept signal data from four input ports (generally from
analog-to-digital converters) and to distribute the data to the DDC blocks. The input interface also has a
user-controlled test generator and noise source, as well as a resampling block. The resampler accepts real inputs
at 3/4rxclk or rxclk rate, mixes down by Fs/4, low-pass filters, and decimates to rxclk/2. This is useful for handling
data at 3/4 rxclk rate (for example, a 92.16-MSPS adcclk rate with a 122.88-MHz rxclk). It is also useful to process
more than 12 CDMA signals when sampling at rxclk rate.
The rx_distribution bus distributes the four channels of signal data to each of the 12 DDC blocks.
Each DDC block selects one of the four channels from the rx_distribution bus and then performs downconversion
tuning, programmable delay, channel filtering with decimation, power measurement, fixed gain adjust, and automatic
gain control. Each DDC block can support one UMTS channel or two CDMA channels. An optional mode permits
stacking two DDC blocks to provide double-length channel filtering. Tuned, filtered, and decimated signal data is
output in bit serial format.
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