GC5316_14 Datasheet, PDF (6/76 Pages) Texas Instruments – HIGH-DENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER

GC5316
SLWS154A − JANUARY 2004 − REVISED MARCH 2004
Resampler Decimate by 2
www.ti.com
a dcclk
4
adcclk
rxclk
=1
rxin_a (or c)
@ adcclk
16 _I
Q
LP F
12 tap
18 _I
2 ¹⁸ _Q
rx_ distribution
bus b (or d)
bus a (or c)
@ rxclk/2
Figure 4. Resampler Decimate by 2 Mode
The decimate by 2 mode permits input data rates up to the rxclk rate (adcclk frequency equals rxclk frequency). This
is useful for processing up to two real inputs at the rxclk rate and extracting more than 12 CDMA signals. A 12-tap
low-pass decimation filter with programmable 18-bit coefficients removes alias images that would fold into the
passband prior to decimation. Table 3 shows the performance of filters designed for various bandwidths when the
resampler is decimating by 2. Table 3 also shows the resulting passband frequencies assuming the input data rate
is 122.88 MHz. Each horizontal row is a unique 12-tap filter which is available on the web.
Table 3. Resampler Filter Performance in the Decimate by 2 Mode
GENERAL APPLICATION
PASSBAND
of clk
0.06
0.07
0.08
0.09
0.1
0.11
0.12
0.13
0.14
RIPPLE
dB
0
0
0
0.01
0.02
0.05
0.09
0.16
0.28
STOPBAND
dB
−109.8
−98.8
−93.4
−89.2
−81.5
−76.8
−71.4
−66.5
−61.8
EXAMPLE APPLICATION
adclk: 122.88 MHz
BANDWIDTH F LOWER F CENTER
MHz
MHz
MHz
14.7
23.3
30.72
17.2
22.1
30.72
19.7
20.9
30.72
22.1
19.7
30.72
24.6
18.4
30.72
27
17.2
30.72
29.5
16
30.72
31.9
14.7
30.72
34.4
13.5
30.72
F UPPER
MHz
38.1
39.3
40.6
41.8
43
44.2
45.5
46.7
47.9
The output of this processing block is complex at rxclk/2 and goes through the selector to drive the rx_distribution
bus. I data for channel rxin_a is routed to a selector driving DDC bus 1, the Q data is input to a selector driving DDC
bus 0. I data for channel rxin_c is routed to a selector driving DDC bus 3, the Q data is input to a selector driving DDC
bus 2.
Table 4. Programming
VARIABLE
resampler_ena
resampler_decim
rate_sel
ssel_rxin(2:0)
ssel_resamp(2:0)
ssel_adc_fifo(2:0)
remix_only
resampler
coefficients
DESCRIPTION
When asserted, turns on the resamplers on input ports rxin_a and rxin_c.
1 = decimate by 1.5x, 0 = decimate by 2x
This selects the FIFO output rate when adc_fifo_bypass = 0. When using the resampler, this value should be
programmed to a 0. When set to 0, the FIFO output is clocked by rxclk (gated if resampler is on and decimating by
1.5). When set to 1, the FIFO output rate is 1/2 of rxclk rate. When set to 2, the FIFO output rate is 1/4 of rxclk rate,
and when set to 3, the FIFO output is at 1/8 of rxclk rate. e.g.: With rxclk 122.88MHz, set rate_sel to 0, 1, 2, or 3
respectively for adcclk 122.88, 61.44, 30.72, or 15.36 MHz.
Synchronizes the rx_distribution bus source and destination and clock generation in each of the DDC blocks.
Synchronizes the resampler Fs/4 mixer and decimation.
Synchronizes the FIFO read and write pointers (fifo depth).
Set to 0 for complex input data, or to 1 for real data. Set this value to 0 when using the resampler. Note that mixed ral
and complex input is not allowed.
The resample’s 18-bit coefficients are loaded by the software cmd5316. The user must provide a coefficient file with
one integer coefficient per line.
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