NS16C2552 Datasheet, PDF (7/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

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Reg
Addr
A2-A0
RD/
WR
RBR
R/W
THR
0x0
Default
IER
R/W
0x1
Default
IIR
R
0x2
Default
FCR
W
0x2
Default
LCR
R/W
0x3
Default
MCR
R/W
0x4
Default
LSR
R
0x5
Default
MSR
R
0x6
Default
SCR
R/W
0x7
Default
DLL
R/W
0x0
Default
DLM
R/W
0x1
Default
AFR
R/W
0x2
Default
DREV
R
0x0
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Table 2. NS16C2552 Register Summary
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
UART 16C550 Compatible Registers (Default Values Upon Reset)
Data7
Data6
Data5
Data4
Data3
Data2
Data1
BIT 0 Comment
Data0
X
CTS Int
Ena
0
FIFOs
Ena
0
RX FIFO
Trigger
0
Divisor
Ena
0
Clk Div
Sel
0
Rx FIFO
Gbl Err
0
DCD
Input
DCD
SCR
Bit 7
1
DLL
Bit 7
X
DLM
Bit 7
X
Rsrvd
Bit 7
0
ID
Bit 7
X
RTS Int
Ena
0
FIFOs
Ena
0
RX FIFO
Trigger
0
Set Tx
Break
0
IR Md
Ena
0
THR &
TSR
Empty
1
RI
Input
RI
SCR
Bit 6
1
DLL
Bit 6
X
DLM
Bit 6
X
Rsrvd
Bit 6
0
ID
Bit 6
X
Xoff Int
Ena
0
INT Src
Bit 5
0
Tx FIFO
Trigger
(2752)
0
Set
Parity
X
Sleep Md
Ena
0
INT Src
Bit 4
0
Tx FIFO
Trigger
(2752)
0
Even
Parity
X
Modem
Stat Int
Ena
0
INT Src
Bit 3
0
DMA Md
Ena
0
Parity
Ena
0
Xon
Any
0
THR E
mpty
0
Internal
Loopbk
Ena
0
Rx
Break
0
OUT2
0
Rx Frame
Error
1
0
0
DSR
Input
CTS
Input
Delta
DCD
DSR
CTS
0
SCR
SCR
SCR
Bit 5
Bit 4
Bit 3
1
1
1
Baud Rate Generator Divisor
DLL
DLL
DLL
Bit 5
Bit 4
Bit 3
X
X
X
DLM
DLM
DLM
Bit 5
Bit 4
Bit 3
X
X
X
Rsrvd
Rsrvd
Rsrvd
Bit 5
0
ID
Bit 5
Bit 4
0
ID
Bit 4
Bit 3
0
DREV
Bit 3
X
RX Line
Stat Int
Ena
0
INT Src
Bit 2
0
Tx FIFO
Reset
X
Tx Empty
Int Ena
X
Rx Data
Int Ena
0
INT Src
Bit 1
0
Rx FIFO
Reset
0
INT Src
Bit 0
LCR[7] = 0
1
FIFOs Ena
0
Stop
Bits
0
OUT1
0
Rx Parity
Error
0
Delta
RI
0
SCR
Bit 2
1
0
Word
Length
Bit 1
0
RTS
Output
Control
0
Rx
Overrun
Error
0
Delta
DSR
0
SCR
Bit 1
1
0
Word
Length
Bit 0
0
DTR
Output
Control
0
Rx Data
Ready
0
Delta
CTS
0
SCR
Bit 0
1
LCR !=
0xBF
DLL
Bit 2
X
DLM
Bit 2
X
RXRDY
DLL
Bit 1
X
DLM
Bit 1
X
BAUDOUT
Sel
0
DREV
Bit 2
Sel
0
DREV
Bit 1
DLL
Bit 0
X
DLM
Bit 0
X
Con-
current
WR
0
DREV
Bit 0
LCR[7] = 1
LCR !
0xBF
LCR[7] = 1
LCR !=
0xBF
DLL =
0x00
DLM =
0x00
Copyright © 2006–2013, Texas Instruments Incorporated
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