NS16C2552 Datasheet, PDF (37/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
DIFFERENCES BETWEEN THE PC16552D AND NS16C2552/2752
The following are differences between the versions of UART that helps user to identify the feature differences.
Table 31. Differences among the UART products
Features
Tx and Rx FIFO sizes
Supply voltage
Highest baud rate
Highest clock input frequency
Operating temperature
Enhanced Register Set
Sleep mode IER[4]
Xon, Xoff, and Xon-Any software auto flow control
CTS and RTS hardware auto flow control
Interrupt source ID in IIR
Tx FIFO trigger level select FCR[5:4]
IrDA v1.0 mode MCR[6]
Clock divisor 1 or 4 select MCR[7]
PC16552D
16-byte
4.5V to 5.5V
1.5Mbps
24MHz
0 - 70°C
No
No
No
No
3-bit
1 level
No
No
NS16C2552
16-byte
2.97V to 5.5V
5.0Mbps
80MHz
-40 to 85°C
Yes
Yes
Yes
Yes
5-bit
1 level
Yes
Yes
NS16C2752
64-byte
2.97V to 5.5V
5.0Mbps
80MHz
-40 to 85°C
Yes
Yes
Yes
Yes
5-bit
4 levels
Yes
Yes
NOTES ON TX FIFO OF NS16C2752
Notes on interrupt assertion and deassertion.
1. To avoid frequent interrupt request generation, there is a hysteresis of two characters. When the transmit
FIFO threshold is enabled and the number of empty spaces reaches the threshold, a THR empty interrupt is
generated requesting the CPU to fill the transmit FIFO. The host has to fill at least two characters in the Tx
FIFO before another THR empty interrupt can be generated.
– The DMA request TXRDY works differently. When the number of empty spaces exceeds the threshold,
TXRDY asserts initiating the DMA transfer. The TXRDY deasserts when the transmit FIFO is full.
2. When the number of empty spaces reaches the threshold level, an interrupt is generated. If the host does not
fill the FIFO, the interrupt will remain asserted until the host writes to the THR or reads from IIR.
3. When the number of empty spaces reaches the threshold level, an interrupt is generated. If the host reads
the IIR but does not fill the Tx FIFO, the INTR is deasserted. However, if the host still does not fill the Tx
FIFO, the FIFO becomes empty. The THR empty interrupt is not generated because the host has not written
to the Tx FIFO and the interrupt service is not complete.
4. When the number of empty spaces reaches the threshold level, a THR empty interrupt is generated. If the
host writes at least one character into the Tx FIFO, the interrupt is serviced and the THR empty flag is
deasserted. Subsequently, if the host fails to fill the FIFO before it reaches empty, a THR empty interrupt will
be asserted.
5. Reset Tx FIFO causes a THR empty interrupt.
Copyright © 2006–2013, Texas Instruments Incorporated
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