NS16C2552 Datasheet, PDF (6/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Register Set
There are two identical register sets, one for each channel, in the DUART. All register descriptions in this section
apply to the register sets in both channels.
To clarify the descriptions of transmission and receiving operations, the nomenclatures through out this
documentation are as follows:
• Frame - Refers to all the bits between Start and Stop.
• Character or word - The payload of a frame, between 5 to 8 bits.
• “!=” - Not equal to.
• Res - Reserved bit.
The address and control pins to register selection is summarized in Table 1.
Table 1. Basic Register Addresses
DLAB1
CHSL
A2
A1
A0
Register
0
1
0
0
0
Receive Buffer (Read), Transmitter Holding Register (Write)
0
1
0
0
1
Interrupt Enable
0
1
0
1
0
Interrupt Identification (Read)
C
0
1
0
1
0
FIFO Control (Write)
H
x
1
0
1
1
Line Control
A
N
x
1
1
0
0
Modem Control
N
x
1
1
0
1
Line Status (Read)
E
L
x
1
1
1
0
Modem Status (Read)
1
x
1
1
1
1
Scratchpad
1
1
0
0
0
Divisor Latch (Least Significant Byte)
1
1
0
0
1
Divisor Latch (Most Significant Byte)
1
1
0
1
0
Alternate Function
DLAB1
CHSL
A2
A1
A0
Register
0
0
0
0
0
Receive Buffer (Read), Transmitter Holding Register (Write)
0
0
0
0
1
Interrupt Enable
0
0
0
1
0
Interrupt Identification (Read)
C
H
0
0
0
1
0
FIFO Control (Write)
A
x
0
0
1
1
Line Control
N
N
x
0
1
0
0
Modem Control
E
x
0
1
0
1
Line Status (Read)
L
2
x
0
1
1
0
Modem Status (Read)
x
0
1
1
1
Scratchpad
1
0
0
0
0
Divisor Latch (Least Significant Byte)
1
0
0
0
1
Divisor Latch (Most Significant Byte)
1
0
0
1
0
Alternate Function
6
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