NS16C2552 Datasheet, PDF (24/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
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After the first character is read by the host, the next character is loaded into the RBR and the error flags are
loaded into LSR[4:2].
DMA Mode
In the FIFO mode, the RXRDY asserts when the character in the Rx FIFO reaches the trigger threshold or
timeout occurs. The RXRDY initiates DMA transfer in a burst mode. The RXRDY deasserts when the Rx FIFO is
completely emptied and the DMA transfer stops (Figure 7.)
Figure 7. RXRDY in DMA Mode 1
Receive in non-FIFO Mode
Interrupt Mode
In the non-FIFO mode, FCR[0]=0, RBR can be configured to generate an IIR Receive Data Available interrupt
IIR[2] immediately after the first byte is received. Upon interrupt, the CPU host reads the RBR and clears the
interrupt. The interrupt is reasserted when the next character is received. (Figure 8.)
Figure 8. Rx Non-FIFO Mode
DMA Mode
In the non-FIFO mode, the presence of a received character in RBR causes the assertion of RXRDY at which
point DMA transfer can be initiated. Upon transfer completion RXRDY is deasserted. DMA transfer stops and
awaits for the next character. (Figure 9.)
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