NS16C2552 Datasheet, PDF (14/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
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MODEM CONTROL REGISTER (MCR)
This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).
There is a clock divider for each channel. Each is capable of taking a common clock input from DC to 80 MHz
and dividing the clock frequency by 1 (default) or 4 depending on the MCR[7] value. The clock divider and the
internal clock division flow is shown in Figure 3.
Figure 3. Internal Clock Dividers
Table 11. MCR (0x4)
Bit
Bit Name
R/W
Def
Description
7
Clk Divider R/W Clock Divider Select
Sel
0 This bit selects the clock divider from crystal or oscillator input. The divider output connects to the Baud
Rate Generator.
1 = Divide XIN frequency by 4.
0 = Divide XIN frequency by 1 (default).
6
IR Mode Sel R/W Infrared Encoder/Decoder Select
0 This bit selects standard modem or IrDA interface.
1 = Infrared IrDA Tx/Rx. The data input and output levels complies to the IrDA infrared interface. The Tx
output is at logic 0 during the idle state.
0 = Standard modem Tx/Rx (default).
5
Xon-Any R/W Xon-Any Enable
Ena
0 This bit enables Xon-Any feature.
1 = Enable Xon-Any function. When Xon/Xoff flow control is enabled, the transmission resumes when
any character is received. The received character is loaded into the Rx FIFO except for Xon or Xoff
characters.
0 = Disable Xon-Any function (default).
4
Internal
R/W Internal Loopback Enable
Loopback
Ena
0 This bit provides a local loopback feature for diagnostic testing of the associated serial channel. (Refer
to INTERNAL LOOPBACK MODE and Figure 15.)
1 = the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state; the receiver Serial Input
(SIN) is disconnected; the output of the Transmitter Shift Register is looped back into the Receiver Shift
Register input; the four MODEM Control inputs (DSR, CTS, RI, and DCD) are disconnected; the four
MODEM Control outputs (DTR, RTS, OUT1 and OUT2) are internally connected to the four MODEM
Control inputs; and the MODEM Control output pins are forced to their inactive state (high). In this
diagnostic mode, data that is transmitted is immediately received. This feature allows the processor to
verify transmit and receive data paths of the DUART. In this diagnostic mode, the receiver and
transmitter interrupts are fully operational. Their sources are external to the part. The MODEM Control
Interrupts are also operational, but the interrupt sources are now the lower four bits of the MODEM
Control Register instead of the four MODEM Control inputs. The interrupts are still controlled by the
Interrupt Ena
0 = Normal Tx/Rx operation; loopback disabled (default).
14
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