NS16C2552 Datasheet, PDF (39/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
AC SPECIFICATIONS (continued)
TA = -40°C to +85°C, V_CC = +2.97V to 5.5V, V_SS = 0V, unless otherwise specified.
Typical specifications are at TA=25°C, and represent most likely parametric norms at the time of product characterization.
The typical specifications are not ensured.
Symbol Parameter
Condition
3.3V Limits
5.0V Limits
Units
Min
Max
Min
Max
t_RST
Reset Pulse Width
n
Baud Rate Divisor
70
70
ns
1
2¹⁶-1
1
2¹⁶-1
B_CLK
Baud Clock
16 x of data rate
1/16 of a bit duration
Host Interface
t_AR
Address Setup Time
t_RA
Address Hold Time
t_RD
RD Strobe Width
t_DY
Read Cycle Delay
t_RDV
Data Access Time
t_HZ
Data Disable Time
t_WR
WR Strobe Width
t_DY
Write Cycle Delay
t_DS
Data Setup Time
t_DH
Data Hold Time
10
10
ns
1
1
ns
35
24
ns
35
24
ns
35
24
ns
0
18
0
18
ns
35
24
ns
35
24
ns
12
12
ns
4
4
ns
Modem Control
t_MDO
t_SIM
Delay from WR to Output
Delay from Modem input to
Interrupt output
20
15
ns
20
15
ns
t_RIM
Delay to Reset interrupt from RD
falling edge
23
17
ns
t_SINT
t_RINT
Line Receive and Transmit
Delay from Stop to Interrupt Set
(1)
4
Delay from of RD to Reset
45
Interrupt
4
Bclk
30
ns
t_STI
Delay from center of Start to INTR
Set
16
10
ns
t_WST
Delay from WR to Transmit Start
0
16
0
16
Bclk
t_HR
Delay from WR to interrupt clear
34
22
ns
DMA Interface
t_WXI
Delay from WR to TXRDY rising
edge
27
18
ns
t_SXA
Delay from Center of Start to
TXRDY falling edge
8
8
Bclk
t_SSR
Delay from Stop to RXRDY falling
edge
4
4
Bclk
t_RXI
Delay from /RD to RXRDY rising
edge
27
18
ns
(1) The B_CLK period decreases with increasing reference clock input. At higher clock input frequency, the number of B_CLK increases.
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