NS16C2552 Datasheet, PDF (32/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Design Notes
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DEBUGGING HINTS
Although the UART device is fairly straight forward, there are cases that when device does not behave as
expected. The normal trouble shooting steps should include the following.
1. Check power supply voltage and make sure it is within the operating range.
2. Check device pin connections against the datasheet pin list.
3. Check an unpopulated printed circuit board (PCB) against the schematic diagram for any shorts.
4. Check the device clock input. For oscillator input, the scope probe can be attached to Xin to verify the clock
voltage swing and frequency. For crystal connection, attach the scope probe to Xout to check for the
oscillation frequency.
5. Reset should be active high and normally low.
6. Use internal loopback mode to test the CPU host interface. If loopback mode is not working, check the CPU
interface timing including read and write bus timing.
7. If loopback mode is getting the correct data, check serial data output and input. The transmit and receive
data may be looped back externally to verify the data path integrity.
CLOCK FREQUENCY ACCURACY
In the UART transmission, the transmitter clock and the receive clock are running in two different clock domains
(unlike in some communication interface that the received clock is a copy of the transmitter clock by sharing the
same clock or by performing clock-data-recovery). Not only the local oscillator frequency, but also the clock
divisor may introduce error in between the transmitter and receiver’s baud rate. The question is how much error
can be tolerated and does not cause data error?
The UART receiver has an internal sampling clock that is 16X the data rate. The sampling clock allows data to
be sampled at the 6/16 to 7/16 point of each bit. The following is an example of a 8-bit data packet with a start, a
parity, and one stop bit. (Figure 16)
Figure 16. Nominal Mid-bit Sampling
If a receiver baud rate generator deviates from the nominal baud rate by Δf, where 1/Δf = ΔT, the first sampling
point will deviate from the nominal sample point by 0.5ΔT. Consequently, the second sampling point will deviate
by 1.5ΔT, 3rd will deviate by 2.5ΔT, and the last bit of a packet with L length (in number of bits) will deviate by
(L − 0.5) x ΔT
In this example, L=11, so that the last bit will deviate by
(11 − 0.5) x ΔT = 10.5ΔT(Figure 17)
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