NS16C2552 Datasheet, PDF (15/50 Pages) National Semiconductor (TI) – Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate

NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Table 11. MCR (0x4) (continued)
Bit
Bit Name
R/W
Def
Description
3
OUT2
R/W Output2
0 This bit controls the Output 2 (OUT2) signal, which is an auxiliary user-designated output. Bit 3 affects
the OUT2 pin as described below. The function of this bit is multiplexed on a single output pin with two
other functions: BAUDOUT and RXDRY. The OUT2 function is the default function of the pin after a
master reset. See ALTERNATE FUNCTION REGISTER (AFR) for more information about selecting one
of these 3 pin functions.
1 = Force OUT2 to logic 0.
0 = Force OUT2 to logic 1 (default).
2
OUT1
R/W Output1
0 In normal operation, OUT1 bit is not available as an output.
In internal Loopback Mode (MCR 0x4.4=1) this bit controls the state of the modem input RI in the MSR
bit 6.
1 = MSR 0x06.6 is at logic 1.
0 = MSR 0x06.6 is at logic 0.
1
RTS Output R/W RTS Output Control
0 This bit controls the RTS pin. If modem interface is not used, this output is used as a general purpose
output.
1 = Force RTS pin to logic 0.
0 = Force RTS pin to logic 1(default).
0
DTR Output R/W DTR Output Control
0 This bit controls the DTR pin. If modem interface is not used, this output is used as a general purpose
output.
1 = Force DTR pin to logic 0.
0 = Force DTR pin to logic 1(default).
LINE STATUS REGISTER (LSR)
This register provides status information to the CPU concerning the data transfer.
Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any of the
corresponding conditions are detected and the interrupt is enabled.
Table 12. LSR (0x5)
Bit
Bit Name
R/W
Def
Description
7
Rx FIFO Err
R Rx FIFO Data Error
0
This bit is a global Rx FIFO error flag. In the 16450 Mode this bit is 0.
1 = A sum of all error bits in the Rx FIFO. These errors include parity, framing, and break indication
in the FIFO data.
0 = No Rx FIFO error (default).
Note: The Line Status Register is intended for read operations only. Writing to this register is not
recommended as this operation is only used for factory testing.
6
THR & TSR
Empty
R THR and TSR Empty
1
This bit is the Transmitter Empty (TEMT) flag.
1 = Whenever the Transmitter Holding Register (THR) (or the Tx FIFO in FIFO mode) and the
Transmitter Shift Register (TSR) are both empty (default).
0 = Whenever either the THR (or the Tx FIFO in FIFO mode) or the TSR contains a data word.
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