DS90UB901Q Datasheet, PDF (7/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

Pin Name
Pin No.
PASS
31
FPD-LINK III INTERFACE
RIN+
35
RIN-
36
CMLOUTP
32
CMLOUTN
33
POWER AND GROUND
VDDSSCG
4
VDDIO1/2/3
VDDD
VDDR
VDDCML
VDDPLL
25, 16, 8
13
30
34
38
VSS
DAP
I/O, Type
Output,
LVCOMS
Description
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Input/Output,
CML
Input/Output,
CML
Output, CML
Output, CML
Non-inverting differential input, bidirectional control channel output. The
interconnect must be AC Coupled with a 100 nF capacitor.
Inverting differential input, bidirectional control channel output. The interconnect
must be AC Coupled with a 100 nF capacitor.
Non-inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
Inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
Power, Digital
Power, Digital
Power, Digital
Power, Analog
Power, Analog
Power, Analog
Ground, DAP
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
LVTTL I/O Buffer Power, The single-ended outputs and control input are powered
from V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Digital Core Power, 1.8V ±5%
Rx Analog Power, 1.8V ±5%
Bidirectional Channel Driver Power, 1.8V ±5%
PLL Power, 1.8V ±5%
DAP must be grounded. DAP is the large metal contact at the bottom side, located
at the center of the LLP package. Connected to the ground plane (GND) with at
least 16 vias.
7
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