DS90UB901Q Datasheet, PDF (12/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
t_RCP
Receiver Output Clock Period t_RCP = t_TCP
PCLK
t_PDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or PCLK
Time
3.0V to 3.6V,
t_CHL
LVCMOS High-to-Low Transition ^C_L ^{= 8 pF (lumped load)}
Time
Default Registers
(Figure 14) (Note 10)
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or ROUT[13:0],
Time
3.0V to 3.6V,
HSYNC, VSYNC
t_CHL
LVCMOS High-to-Low Transition ^C_L ^{= 8 pF (lumped load)}
Time
Default Registers
(Figure 14) (Note 10)
t_ROS
ROUT Setup Data to PCLK
V_DDIO: 1.71V to 1.89V or ROUT[13:0],
t_ROH
ROUT Hold Data to PCLK
3.0V to 3.6V,
HSYNC, VSYNC
C_L = 8 pF (lumped load)
Default Registers
(Figure 16)
t_DD
Deserializer Delay
Default Registers
Register 0x03h b[0]
(RRFB = 1)
(Figure 15)
10 MHz–43 MHz
t_DDLT
t_RJIT
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
(Figure 13) (Note 5)
(Figure 17, Figure 19)
(Note 13, Note 14)
10 MHz–43 MHz
43 MHz
t_RCJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF
(Note 6, Note 10)
10 MHz
43 MHz
t_DPJ
Deserializer Period Jitter
PCLK
SSCG[3:0] = OFF
(Note 7, Note 10)
10 MHz
43 MHz
t_DCCJ
Deserializer Cycle-to-Cycle Clock PCLK
Jitter
SSCG[3:0] = OFF
(Note 8, Note 10)
10 MHz
43 MHz
fdev
fmod
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
LVCMOS Output Bus
SSC[3:0] = ON
(Figure 20)
20 MHz–43 MHz
20 MHz–43 MHz
Min
Typ Max
23.3
T
100
45
50
55
1.3
2.0
2.8
1.3
2.0
2.8
1.6
2.4
3.3
1.6
2.4
3.3
0.38T 0.5T
0.38T 0.5T
4.571T 4.571T 4.571T
+8
+ 12 + 16
10
0.53
300
550
120
250
425
600
320
480
320
500
300
500
±0.5% to
±2.0%
9 kHz to
66 kHz
Units
ns
%
ns
ns
ns
ns
ms
UI
ps
ps
ps
%
kHz
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