DS90UB901Q Datasheet, PDF (29/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

FIGURE 23. Read Byte
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FIGURE 24. Basic Operation
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FIGURE 25. START and STOP Conditions
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SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote de-
vices on the I2C bus through the bidirectional control channel,
slave clock stretching must be supported by the I2C master
controller/MCU. The chipset utilizes bus clock stretching
(holding the SCL line low) during data transmission; where
the I2C slave pulls the SCL line low prior to the 9th clock of
every I2C data transfer (before the ACK signal). The slave
device will not control the clock and only stretches it until the
remote peripheral has responded.
Any remote access involves the clock stretching period fol-
lowing the transmitted byte, prior to completion of the ac-
knowledge bit. Since each byte transferred to the I2C slave
must be acknowledged separately, the clock stretching will be
done for each byte sent by the host controller. For remote
accesses, the “Response Delay” shown is on the order of 12
µs (typical). See Application Note AN-2173 / SNLA131 for
more details.
ID[X] ADDRESS DECODER
The ID[x] pin is used to decode and set the physical slave
address of the Serializer/Deserializer (I²C only) to allow up to
six devices on the bus using only a single pin. The pin sets
one of six possible addresses for each Serializer/Deserializer
device. The pin must be pulled to VDD (1.8V, NOT VDDIO))
with a 10 kΩ resistor and a pull down resistor (RID) of the
recommended value to set the physical device address. The
recommended maximum resistor tolerance is 0.1% worst
case (0.2% total tolerance).
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