DS90UB901Q Datasheet, PDF (4/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB901Q Serializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[13:0]
32, 31, 30, 29, Inputs, LVCMOS Parallel data inputs.
27, 26, 24, 23, w/ pull down
22, 21, 20, 19,
18, 17
HSYNC
1
Inputs, LVCMOS Horizontal SYNC Input
w/ pull down
VSYNC
2
Inputs, LVCMOS Vertical SYNC Input
w/ pull down
PCLK
3
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
GPIO[5:2]
20, 19, 18, 17 Input/Output, DIN[3:0] general-purpose pins can be individually configured as either inputs or
LVCMOS outputs; used to control and respond to various commands.
GPIO[1:0]
16, 15
Input/Output, General-purpose pins can be individually configured as either inputs or outputs;
LVCMOS used to control and respond to various commands.
BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
MODE
4
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pull-up resistor to V_DDIO.
5
Input/Output, Data line for the bidirectional control bus communication
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I²C Mode select
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Input, LVCMOS
8
Standby mode and is enabled through remote wakeup by Deserializer)
w/ pull down
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I²C
controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
ID[x]
Device ID Address Select
6
Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
9
Input, LVCMOS
w/ pull down
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
RES
7
Input, LVCMOS Reserved.
w/ pull down This pin MUST be tied LOW.
FPD-LINK III INTERFACE
DOUT+
13
Input/Output, Non-inverting differential output, bidirectional control channel input. The
CML
interconnect must be AC Coupled with a 100 nF capacitor.
DOUT-
12
Input/Output, Inverting differential output, bidirectional control channel input. The interconnect
CML
must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDPLL
10
Power, Analog PLL Power, 1.8V ±5%
VDDT
11
Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML
14
Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD
28
Power, Digital Digital Power, 1.8V ±5%
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