DS90UB901Q Datasheet, PDF (6/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB902Q Deserializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[13:0]
9, 10, 11, 12,
14, 15, 17, 18,
19, 20, 21, 22,
23, 24
Outputs,
LVCMOS
Parallel data outputs.
HSYNC
7
Output,
Horizontal SYNC Output
LVCMOS
VSYNC
6
Output,
Vertical SYNC Output
LVCMOS
PCLK
5
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT OUTPUT (GPIO)
ROUT[3:0] /
GPIO[5:2]
21, 22, 23, 24
Input/Output,
LVCMOS
ROUT[3:0] general-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
GPIO[1:0]
26, 27
Input/Output, General-purpose pins can be individually configured as either inputs or outputs;
LVCMOS used to control and respond to various commands.
BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
3
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pull-up resistor to V_DDIO.
2
Input/Output, Data line for bidirectional control bus communication
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I²C Mode select
MODE
MODE = L, Master mode; Device generates and drives the SCL clock line, where
40
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
w/ pull up MODE = H, Slave mode (default); Device accepts SCL clock input and attached to
an I²C controller master on the bus. Slave mode does not generate the SCL clock,
but uses the clock generated by the Master for the data transfers.
ID[x]
Device ID Address Select
1
Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
29
Input, LVCMOS ^{PDB = H, Deserializer is enabled and is ON.}
w/ pull down ^{PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power}
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK
LOCK Status Output Pin.
28
Output,
LVCMOS
LOCK = H, CDR/PLL is Locked, outputs are active
LOCK = L, CDR/PLL is unlocked, the LVCMOS Outputs depend on OSS_SEL
control register, the CDR/PLL is shutdown and IDD is minimized. May be used as
Link Status.
PASS
When BISTEN = L; Normal operation
31
Output,
LVCOMS
PASS is high to indicate no errors are detected. The PASS pin asserts low to
indicate a CRC error was detected on the Link.
Reserved
RES
32, 33, 39
-
Pin 39: This pin MUST be tied LOW.
Pins 32,33: Route to test point or leave open if unused. See also FPD-LINK III
INTERFACE pin description section.
BIST MODE
BISTEN
BIST Enable Pin.
37
Input, LVCMOS
w/ pull down
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
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