DS90UB901Q Datasheet, PDF (28/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

Functional Description
The DS90UB901Q/902Q FPD-Link III chipset is intended for
camera applications. The Serializer/ Deserializer chipset op-
erates from a 10 MHz to 43 MHz pixel clock frequency. The
DS90UB901Q transforms a 16-bit wide parallel LVCMOS da-
ta bus along with a bidirectional control bus into a single high-
speed differential pair. The high-speed serial bit stream
contains an embedded clock and DC-balance information
which enhances signal quality to support AC coupling. The
DS90UB902Q receives the single serial data stream and con-
verts it back into a 16-bit wide parallel data bus together with
the bidirectional control channel data bus.
The bidirectional control channel of the DS90UB901Q/902Q
provides bidirectional communication between the image
sensor and Electronic Control Unit (ECU) over the same dif-
ferential pair used for video data interface. This interface
offers advantages over other chipsets by eliminating the need
for additional wires for programming and control. The bidirec-
tional control channel bus is controlled via an I²C port. The
bidirectional control channel offers asymmetrical communi-
cation and is not dependent on video blanking intervals.
SERIAL FRAME FORMAT
The DS90UB901Q/902Q chipset will transmit and receive a
pixel of data in the following format:
FIGURE 21. Serial Bitstream for 28-bit Symbol
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The High Speed Forward Channel is a 28-bit symbol com-
posed of 16 bits of data containing camera data & control
information transmitted from Serializer to Deserializer. CLK1
and CLK0 represent the embedded clock in the serial stream.
CLK1 is always HIGH and CLK0 is always LOW. This data
payload is optimized for signal transmission over an AC cou-
pled link. Data is randomized, balanced and scrambled. The
data payload may be checked using a 4-bit CRC function. The
CRC monitors the link integrity of the serialized data and re-
ports when an error condition is detected.
The bidirectional control channel data is transferred along
with the high-speed forward data over the same serial link.
This architecture provides a full duplex low speed back chan-
nel across the serial link together with a high speed forward
channel without the dependence of the video blanking phase.
DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND
I2C MODES
The I²C compatible interface allows programming of the
DS90UB901Q, DS90UB902Q, or an external remote device
(such as a camera) through the bidirectional control channel.
Register programming transactions to/from the
DS90UB901Q/902Q chipset are employed through the clock
(SCL) and data (SDA) lines. These two signals have open-
drain I/Os and both lines must be pulled-up to VDDIO by
external resistor. Figure 4 shows the timing relationships of
the clock (SCL) and data (SDA) signals. Pull-up resistors or
current sources are required on the SCL and SDA busses to
pull them high when they are not being driven low. A logic zero
is transmitted by driving the output low. A logic high is trans-
mitted by releasing the output and allowing it to be pulled-up
externally. The appropriate pull-up resistor values will depend
upon the total bus capacitance and operating speed. The
DS90UB901Q/902Q I²C bus data rate supports up to 100
kbps according to I²C specification.
To start any data transfer, the DS90UB901Q/902Q must be
configured in the proper I²C mode. Each device can function
as an I²C slave proxy or master proxy depending on the mode
determined by MODE pin. The Ser/Des interface acts as a
virtual bridge between Master controller (MCU) and the re-
mote device. When the MODE pin is set to High, the device
is treated as a slave proxy; acts as a slave on behalf of the
remote slave. When addressing a remote peripheral or Seri-
alizer/Deserializer (not wired directly to the MCU), the slave
proxy will forward any byte transactions sent by the Master
controller to the target device. When MODE pin is set to Low,
the device will function as a master proxy device; acts as a
master on behalf of the I²C master controller. Note that the
devices must have complementary settings for the MODE
configuration. For example, if the Serializer MODE pin is set
to High then the Deserializer MODE pin must be set to Low
and vice-versa.
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FIGURE 22. Write Byte
28
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