DS90UB901Q Datasheet, PDF (37/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

• The chipset needs to be configured in Camera mode:
Serializer MODE = 0 and Deserializer MODE = 1
• Serializer expects remote wake-up by default at power on.
• Configure the control channel driver of the Deserializer to
be in remote wake-up mode by setting Deserializer
Register 0x26h = 0xC0h.
• Perform remote wake-up on Serializer by setting
Deserializer Register 0x01 b[2] = 1
• Return the control channel driver of the Deserializer to the
normal operation mode by setting Deserializer Register
0x26h = 0x00h
• Configure the control channel driver of the Deserializer to
be in normal operation mode by setting Deserializer
Register 0x27h = 0xC0h.
Serializer can also be put into standby mode by programming
the Deserializer remote wake-up control register 0x01 b[2]
REM_WAKEUP to 0.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the
device. The modes can be controlled by the host and is used
to disable the Link to save power when the remote device is
not operational. An auto mode is also available. In this mode,
the PDB pin is tied High and the SER switches over to an
internal oscillator when the PCLK stops or not present. When
a PCLK starts again, the SER will then lock to the valid input
PCLK and transmits the data to the DES. In powerdown
mode, the high-speed driver outputs are static (High).
The DES has a PDB input pin to ENABLE or Powerdown the
device. This pin can be controlled by the system and is used
to disable the DES to save power. An auto mode is also avail-
able. In this mode, the PDB pin is tied High and the DES will
enter powerdown when the serial stream stops. When the
serial stream starts up again, the DES will lock to the input
stream and assert the LOCK pin and output valid data. In
powerdown mode, the Data and PCLK outputs are set by the
OSS_SEL control register.
POWER UP REQUIREMENTS AND PDB PIN
It is required to delay and release the PDB input signal after
VDD (VDDn and VDDIO) power supplies have settled to the
recommended operating voltages. A external RC network can
be connected to the PDB pin to ensure PDB arrives after all
the VDD have stabilized.
SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order
to compensate for loss from the media. The level of equal-
ization is controlled via register setting. Note this function can
be observed at the CMLOUTP/N test port enabled via the
control registers.
EMI REDUCTION
Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch
in a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes
the number of outputs switching simultaneously and helps to
reduce supply noise. In addition it spreads the noise spectrum
out reducing overall EMI.
Des Spread Spectrum Clocking
The DS90UB902Q parallel data and clock outputs have pro-
grammable SSCG ranges from 9 kHz–66 kHz and ±0.5%–
±2% from 20 MHz to 43 MHz. The modulation rate and mod-
ulation frequency variation of output spread is controlled
through the SSC control registers.
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is
used. For the SER, this register determines the edge that the
data is latched on. If TRFB register is 1, data is latched on the
Rising edge of the PCLK. If TRFB register is 0, data is latched
on the Falling edge of the PCLK. For the DES, this register
determines the edge that the data is strobed on. If RRFB reg-
ister is 1, data is strobed on the Rising edge of the PCLK. If
RRFB register is 0, data is strobed on the Falling edge of the
PCLK.
30113551
FIGURE 35. Programmable PCLK Strobe Select
37
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