DS90UB901Q Datasheet, PDF (23/45 Pages) Texas Instruments – 10 - 43MHz 14 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

TABLE 2. DS90UB902Q Control Registers
Addr
(Hex)
0
1
2
Name
I²C Device ID
Reset
RESERVED
Auto Clock
OSS Select
SSCG
Bits
Field
R/W Default
Description
7:1 DEVICE ID
RW 0xC0'h 7-bit address of Deserializer;
0x60h
(1100_000X) default
0 DES ID SEL
0: Device ID is from ID[x]
1: Register I²C Device ID overrides ID[x]
7:3 RESERVED
0x00'h Reserved
2 REM_WAKEUP
RW
Remote Wake-up Select
1: Enable
Generate remote wakeup signal automatically wake-up
0 the Serializer in Standby mode
0: Disable
Puts the Serializer (MODE = 0) in Standby mode when
Deserializer MODE = 1
1 DIGITALRESET0
RW
0
1: Resets the device to default register values. Does not
self clear affect device I²C Bus or Device ID
0 DIGITALRESET1
RW
0 1: Digital Reset, retains all register values
self clear
7:6 RESERVED
00'b Reserved
5 AUTO_CLOCK
RW
1: Output PCLK or Internal 25 MHz Oscillator clock
0
0: Only PCLK when valid PCLK present
4 OSS_SEL
Output Sleep State Select
RW
0 0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
3:0 SSCG
0000'b
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
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