DS90CR483A_15 Datasheet, PDF (7/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

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AC Timing Diagrams
DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Figure 1. “Worst Case” Test Pattern
Figure 2. DS90CR483A (Transmitter) LVDS Output Load and Transition Times
Figure 3. DS90CR484A (Receiver) CMOS/TTL Output Load and Transition Times
Figure 4. DS90CR483A (Transmitter) Input Clock Transition Time
Figure 5. DS90CR483A (Transmitter) Setup/Hold and High/Low Times
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