DS90CR483A_15 Datasheet, PDF (16/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to TTL signal
• Minimize the number of VIA
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Minimize skew between pairs
• Terminate as close to the RX inputs as possible
FOR MORE INFORMATION
Channel Link Applications Notes currently available:
• AN-1041 Introduction to Channel Link
• AN-1059 RSKM Calculations
• AN-1108 PCB and Interconnect Guidelines
• AN-905 Differential Impedance
• TI’s LVDS Owner’s Manual
Typical Data Rate vs Cable Length Curve
1000
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V_CC = 3.3V, Pre = 100%
100
V_CC = 3.3V, Pre = 0%
10
1 2 3 4 5 6 7 10 1112 1314 15 1617 18
CABLE LENGTH (m)
Figure 17.
Data Rate vs Cable Length Test Procedure
The Data Rate vs Cable Length graph was generated using Texas Instruments’ CLINK3V48BT-112 Evaluation
Kit and 3M’s Mini D Ribbon (MDR) Cable under typical conditions (Vcc = 3.3V, Temp = +25°C). A Tektronix
MB100 Bit-Error-Rate Tester (BERT) was used to send a PRBS (2¹⁵) pattern to 32 of the 48 input channels on
the transmitter (DS90CR483A). The BERT was also used to monitor the corresponding 32 receiver
(DS90CR484A) output channels for bit errors. The frequency of the input signal were increased until bit errors
were reported on the BERT. The frequency on the graph is the highest frequency without error.
16
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