DS90CR483A_15 Datasheet, PDF (10/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
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C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
• Cable Skew — typically 10 ps to 40 ps per foot, media dependent
• TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
• ISI is dependent on interconnect length; may be zero
• See Applications Information section for more details.
Figure 13. Receiver Skew Margin (RSKM) without DESKEW
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
• d = Tppos — Transmitter output pulse position (min and max)
• f = TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
• m = extra margin - assigned to ISI in long cable applications
• See Applications Information section for more details.
Figure 14. Receiver Skew Margin (RSKMD) with DESKEW
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