DS90CR483A_15 Datasheet, PDF (14/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
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CLOCK JITTER
The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very
low cycle-to-cycle jitter is passed on to the transmitter outputs. Cycle-to-cycle jitter has been measured over
frequency to be less than 100 ps with input step function jitter applied. This should be subtracted from the
RSKM/RSKMD budget as shown and described in RSKM - RECEIVER SKEW MARGIN and RSKMD -
RECEIVER SKEW MARGIN WITH DESKEW. This rejection capability significantly reduces the impact of jitter at
the TXinput clock pin, and improves the accuracy of data sampling in the receiver. Transmitter output jitter is
effected by PLLVCC noise and input clock jitter - minimize supply noise and use a low jitter clock source to limit
output jitter. The falling edge of the input clock to the transmitter is the critical edge and is used by the PLL
circuit.
RSKM - RECEIVER SKEW MARGIN
RSKM is a chipset parameter and is explained in AN-1059 in detail. It is the difference between the transmitter’s
pulse position and the receiver’s strobe window. RSKM must be greater than the summation of: Interconnect
skew, LVDS Source Clock Jitter (TJCC), and ISI (if any). Interconnect skew includes PCB traces differences,
connector skew and cable skew for a cable application. PCB trace and connector skew can be compensated for
in the design of the system. Cable skew is media type and length dependant.
RSKMD - RECEIVER SKEW MARGIN WITH DESKEW
RSKMD is a chipset parameter and is applicable when the DESKEW feature of the DS90CR484A is employed. It
is the difference between the receiver’s strobe window and the ideal pulse locations. The DESKEW feature
adjusts for skew between each data channel and the clock channel. This feature is supported up to 80 MHz clock
rate. RSKMD must be greater than the summation of: Transmitter’s Pulse Position variance, LVDS Source Clock
Jitter (TJCC), and ISI (if any). With Deskew, RSKMD is ≥ 25% of TBIT. Deskew compensates for interconnect
skew which includes PCB traces differences, connector skew and cable skew (for a cable application). PCB trace
and connector skew can be compensated for in the design of the system. Note, cable skew is media type and
length dependant. Cable length may be limited by the RSKMD parameter prior to the interconnect skew reaching
1 TBIT in length due to ISI effects.
POWER DOWN
Both transmitter and receiver provide a power down feature. When asserted current draw through the supply pins
is minimized and the PLLs are shut down. The transmitter outputs are in TRI-STATE when in power down mode.
The receiver outputs are forced to a active LOW state when in the power down mode. (See the and Tables). The
PD pin should be driven HIGH to enable the device once V_CC is stable.
CONFIGURATIONS
The transmitter is designed to be connected typically to a single receiver load. This is known as a point-to-point
configuration. It is also possible to drive multiple receiver loads if certain restrictions are made. Only the final
receiver at the end of the interconnect should provide termination across the pair. In this case, the driver still
sees the intended DC load of 100 Ohms. Receivers connected to the cable between the transmitter and the final
receiver must not load down the signal. To meet this system requirement, stub lengths from the line to the
receiver inputs must be kept very short.
CABLE TERMINATION
A termination resistor is required for proper operation to be obtained. The termination resistor should be equal to
the differential impedance of the media being driven. This should be in the range of 90 to 132 Ohms. 100 Ohms
is a typical value common used with standard 100 Ohm twisted pair cables. This resistor is required for control of
reflections and also to complete the current loop. It should be placed as close to the receiver inputs to minimize
the stub length from the resistor to the receiver input pins.
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