DS90CR483A_15 Datasheet, PDF (13/27 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz

DS90CR483A, DS90CR484A
www.ti.com
SNLS291A – APRIL 2008 – REVISED APRIL 2013
Table 2. Pre-emphasis needed per cable length⁽¹⁾
Frequency
112MHz
112MHz
80MHz
80MHz
66MHz
PRE Voltage
1.0V
1.5V
1.0V
1.2V
1.5V
Typical cable length
2 meters
5 meters
2 meters
5+ meters
7 meters
(1) This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable,
length and operating frequency.
2. DC Balance
In addition to data information an additional bit is transmitted on every LVDS data signal line during each cycle
as shown in LVDS Interface. This bit is the DC balance bit (DCBAL). The purpose of the DC Balance bit is to
minimize the short- and long-term DC bias on the signal lines. This is achieved by selectively sending the data
either unmodified or inverted.
The value of the DC balance bit is calculated from the running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall be calculated by subtracting the number of bits of
value 0 from the number of bits value 1 in the current word. Initially, the running word disparity may be any value
between +7 and −6. The running word disparity shall be calculated as a continuous sum of all the modified data
disparity values, where the unmodified data disparity value is the calculated data disparity minus 1 if the data is
sent unmodified and 1 plus the inverse of the calculated data disparity if the data is sent inverted. The value of
the running word disparity shall saturate at +7 and −6.
The value of the DC balance bit (DCBAL) shall be 0 when the data is sent unmodified and 1 when the data is
sent inverted. To determine whether to send data unmodified or inverted, the running word disparity and the
current data disparity are used. If the running word disparity is positive and the current data disparity is positive,
the data shall be sent inverted. If the running word disparity is positive and the current data disparity is zero or
negative, the data shall be sent unmodified. If the running word disparity is negative and the current data
disparity is positive, the data shall be sent unmodified. If the running word disparity is negative and the current
data disparity is zero or negative, the data shall be sent inverted. If the running word disparity is zero, the data
shall be sent inverted.
DC Balance mode is set when the BAL pin on the transmitter is tied HIGH - See the and Tables. DC Balancing is
useful on long cable applications which are typically greater than 5 meters in length.
3. Deskew
Deskew is supported in the DC Balance mode only (BAL = high on DS90CR483A). The “DESKEW” pin on the
receiver when set high will deskew a minimum of ±1 LVDS data bit time skew from the ideal strobe location
between signals arriving on independent differential pairs (pair-to-pair skew). It is required that the “DS_OPT” pin
on the Transmitter must be applied low for a minimum of four clock cycles to complete the deskew operation. It is
also required that this must be performed at least once at any time after the PLLs have locked to the input clock
frequency. If power is lost, or if the cable has been switched, this procedure must be repeated or else the
receiver may not sample the incoming LVDS data correctly. When the receiver is in the deskew mode, all
receiver data outputs are set to a LOW state, but the receiver clock output is still active and switching. Setting
the “DESKEW” pin to low will disable the deskew operation and allow the receiver to operation on a fixed data
sampling strobe. In this case, the ”DS_OPT” pin on the transmitter must then be set high.
The DS_OPT pin at the input of the transmitter (DS90CR483A) is used to initiate the deskew calibration pattern.
It must be applied low for a minimum of four clock cycles in order for the receiver to complete the deskew
operation. For this reason, the LVDS clock signal with DS_OPT applied high (active data sampling) shall be
1111000 or 1110000 pattern. During the deskew operation with DS_OPT applied low, the LVDS clock signal
shall be 1111100 or 1100000 pattern. The transmitter will also output a series of 1111000 or 1110000 onto the
LVDS data lines (TxOUT 0-7) during deskew so that the receiver can automatically calibrated the data sampling
strobes at the receiver inputs. Each data channel is deskewed independently and is tuned with a step size of 1/3
of a bit time over a range of +/−1 TBIT from the ideal strobe location. The Deskew feature operates up to clock
rates of 80 MHz only. If the Receiver is enabled in the deskew mode, then it must be trained before data transfer.
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